參數(shù)資料
型號： MFRC53101T
廠商： NXP Semiconductors N.V.
元件分類： 通信及網(wǎng)絡(luò)
英文描述： ISO-IEC 14443 reader IC
封裝： MFRC53101T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<1<week 51, 2004,;MFRC53101T/0FE<SOT287-1 (SO32)|<<http://www.nxp.com/packages/SOT287-1.html<
文件頁數(shù)： 28/116頁
文件大?。?/td> 862K
代理商： MFRC53101T
MFRC531_34
NXP B.V. 2010. All rights reserved.
Product data sheet
PUBLIC
Rev. 3.4 — 26 January 2010
056634
28 of 116
NXP Semiconductors
MFRC531
ISO/IEC 14443 reader IC
9.7.2
Reset phase
The reset phase automatically follows the Hard power-down. Once the oscillator is
running stably, the reset phase takes 512 clock cycles. During the reset phase, some
register bits are preset by hardware. The respective reset values are given in the
description of each register (see
Section 10.5 on page 48
).
Remark:
When the internal oscillator is used, time (t
osc
) is required for the oscillator to
become stable. This is because the internal oscillator is supplied by V
DDA
and any clock
cycles will not be detected by the internal logic until V
DDA
is stable.
9.7.3
Initialization phase
The initialization phase automatically follows the reset phase and takes 128 clock cycles.
During the initializing phase the content of the EEPROM blocks 1 and 2 is copied into the
register subaddresses 10h to 2Fh (see
Section 9.2.2 on page 13
).
Remark:
During the production test, the MFRC531 is initialized with default configuration
values. This reduces the microprocessor’s configuration time to a minimum.
9.7.4
Initializing the parallel interface type
A different initialization sequence is used for each microprocessor. This enables detection
of the correct microprocessor interface type and synchronization of the microprocessor’s
and the MFRC531’s start-up. See
Section 9.1.3 on page 8
for detailed information on the
different connections for each microprocessor interface type.
During StartUp phase, the command value is set to 3Fh once the oscillator attains clock
frequency stability at an amplitude of > 90 % of the nominal 13.56 MHz clock frequency. At
the end of the initialization phase, the MFRC531 automatically switches to idle and the
command value changes to 00h.
To ensure correct detection of the microprocessor interface, the following sequence is
executed:
the Command register is read until the 6-bit register value is 00h. On reading the 00h
value, the internal initialization phase is complete and the MFRC531 is ready to be
controlled
write 80h to the Page register to initialize the microprocessor interface
read the Command register. If it returns a value of 00h, the microprocessor interface
was successfully initialized
write 00h to the Page registers to activate linear addressing mode.
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