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| 型號(hào)： | MT47H128M8HV-187ELIT:E |
| 元件分類： | DRAM |
| 英文描述： | 128M X 8 DDR DRAM, 0.35 ns, PBGA60 |
| 封裝： | 8 X 11.50 MM, FBGA-60 |
| 文件頁(yè)數(shù)： | 101/133頁(yè) |
| 文件大?。?/td> | 9170K |
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List of Figures
Figure 1: 1Gb DDR2 Part Numbers ................................................................................................................... 3
Figure 2: Simplified State Diagram ................................................................................................................... 9
Figure 3: 256 Meg x 4 Functional Block Diagram ............................................................................................. 12
Figure 4: 128 Meg x 8 Functional Block Diagram ............................................................................................. 13
Figure 5: 64 Meg x 16 Functional Block Diagram ............................................................................................. 14
Figure 6: 60-Ball FBGA – x4, x8 Ball Assignments (Top View) ........................................................................... 15
Figure 7: 84-Ball FBGA – x16 Ball Assignments (Top View) .............................................................................. 16
Figure 8: 84-Ball FBGA Package (8mm x 12.5mm) – x16 ................................................................................... 19
Figure 9: 60-Ball FBGA Package (8mm x 11.5mm) – x4, x8 ............................................................................... 20
Figure 10: 60-Ball FBGA (8mm x 10mm) – x4, x8 ............................................................................................. 21
Figure 11: Example Temperature Test Point Location ..................................................................................... 24
Figure 12: Single-Ended Input Signal Levels ................................................................................................... 44
Figure 13: Differential Input Signal Levels ...................................................................................................... 45
Figure 14: Differential Output Signal Levels .................................................................................................... 47
Figure 15: Output Slew Rate Load .................................................................................................................. 48
Figure 16: Full Strength Pull-Down Characteristics ......................................................................................... 49
Figure 17: Full Strength Pull-Up Characteristics ............................................................................................. 50
Figure 18: Reduced Strength Pull-Down Characteristics ................................................................................. 51
Figure 19: Reduced Strength Pull-Up Characteristics ...................................................................................... 52
Figure 20: Input Clamp Characteristics .......................................................................................................... 53
Figure 21: Overshoot ..................................................................................................................................... 54
Figure 22: Undershoot .................................................................................................................................. 54
Figure 23: Nominal Slew Rate for tIS .............................................................................................................. 59
Figure 24: Tangent Line for tIS ....................................................................................................................... 59
Figure 25: Nominal Slew Rate for tIH .............................................................................................................. 60
Figure 26: Tangent Line for tIH ...................................................................................................................... 60
Figure 27: Nominal Slew Rate for tDS ............................................................................................................. 65
Figure 28: Tangent Line for tDS ...................................................................................................................... 65
Figure 29: Nominal Slew Rate for tDH ............................................................................................................ 66
Figure 30: Tangent Line for tDH ..................................................................................................................... 66
Figure 31: AC Input Test Signal Waveform Command/Address Balls ............................................................... 67
Figure 32: AC Input Test Signal Waveform for Data with DQS, DQS# (Differential) ........................................... 67
Figure 33: AC Input Test Signal Waveform for Data with DQS (Single-Ended) .................................................. 68
Figure 34: AC Input Test Signal Waveform (Differential) ................................................................................. 68
Figure 35: MR Definition ............................................................................................................................... 76
Figure 36: CL ................................................................................................................................................ 79
Figure 37: EMR Definition ............................................................................................................................. 80
Figure 38: READ Latency ............................................................................................................................... 83
Figure 39: WRITE Latency ............................................................................................................................. 83
Figure 40: EMR2 Definition ........................................................................................................................... 84
Figure 41: EMR3 Definition ........................................................................................................................... 85
Figure 42: DDR2 Power-Up and Initialization ................................................................................................. 87
Figure 43: Example: Meeting tRRD (MIN) and tRCD (MIN) .............................................................................. 90
Figure 44: Multibank Activate Restriction ....................................................................................................... 91
Figure 45: READ Latency ............................................................................................................................... 93
Figure 46: Consecutive READ Bursts .............................................................................................................. 94
Figure 47: Nonconsecutive READ Bursts ........................................................................................................ 95
Figure 48: READ Interrupted by READ ........................................................................................................... 96
Figure 49: READ-to-WRITE ............................................................................................................................ 96
Figure 50: READ-to-PRECHARGE – BL = 4 ...................................................................................................... 97
1Gb: x4, x8, x16 DDR2 SDRAM
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. S 10/09 EN
7
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| MT47H128M8HV-25AT | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
| MT47H128M8HV-25EAT | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
| MT47H128M8HV-25EIT | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
| MT47H128M8HV-25EL | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
| MT47H128M8HV-25IT | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
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