- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄224506 > MT47H128M8HV-187ELIT:E 128M X 8 DDR DRAM, 0.35 ns, PBGA60 PDF資料下載
參數(shù)資料
| 型號(hào)： | MT47H128M8HV-187ELIT:E |
| 元件分類： | DRAM |
| 英文描述： | 128M X 8 DDR DRAM, 0.35 ns, PBGA60 |
| 封裝： | 8 X 11.50 MM, FBGA-60 |
| 文件頁(yè)數(shù)： | 70/133頁(yè) |
| 文件大?。?/td> | 9170K |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)當(dāng)前第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)
Table 34 (page 64), and Table 35 (page 64); listed values are already derated for slew
rate variations and converted from baseline values to VREF values.
32. For each input signal—not the group collectively.
33. There are two sets of values listed for command/address: tISa, tIHa and tISb, tIHb. The tISa,
tIHa values (for reference only) are equivalent to the baseline values of tISb, tIHb at VREF
when the slew rate is 1 V/ns. The baseline values, tISb, tIHb, are the JEDEC-defined values,
referenced from the logic trip points. tISb is referenced from VIH(AC) for a rising signal
and VIL(AC) for a falling signal, while tIHb is referenced from VIL(DC) for a rising signal and
VIH(DC) for a falling signal. If the command/address slew rate is not equal to 1 V/ns, then
the baseline values must be derated by adding the values from Table 28 (page 57) and
34. This is applicable to READ cycles only. WRITE cycles generally require additional time
due to tWR during auto precharge.
35. READs and WRITEs with auto precharge are allowed to be issued before tRAS (MIN) is
satisfied because tRAS lockout feature is supported in DDR2 SDRAM.
36. When a single-bank PRECHARGE command is issued, tRP timing applies. tRPA timing ap-
plies when the PRECHARGE (ALL) command is issued, regardless of the number of banks
open. For 8-bank devices (
lists tRP [MIN] + tCK [AVG] MIN).
37. This parameter has a two clock minimum requirement at any tCK.
38. The tFAW (MIN) parameter applies to all 8-bank DDR2 devices. No more than four bank-
ACTIVATE commands may be issued in a given tFAW (MIN) period. tRRD (MIN) restriction
still applies.
39. The minimum internal READ-to-PRECHARGE time. This is the time from which the last 4-
bit prefetch begins to when the PRECHARGE command can be issued. A 4-bit prefetch is
when the READ command internally latches the READ so that data will output CL later.
This parameter is only applicable when tRTP/(2 × tCK) > 1, such as frequencies faster than
533 MHz when tRTP = 7.5ns. If tRTP/(2 × tCK)
≤ 1, then equation AL + BL/2 applies. tRAS
(MIN) has to be satisfied as well. The DDR2 SDRAM will automatically delay the internal
PRECHARGE command until tRAS (MIN) has been satisfied.
40. tDAL = (nWR) + (tRP/tCK). Each of these terms, if not already an integer, should be roun-
ded up to the next integer. tCK refers to the application clock period; nWR refers to the
tWR parameter stored in the MR9–MR11. For example, -37E at tCK = 3.75ns with tWR
programmed to four clocks would have tDAL = 4 + (15ns/3.75ns) clocks = 4 + (4) clocks =
8 clocks.
41. The refresh period is 64ms (commercial) or 32ms (industrial and automotive). This equa-
tes to an average refresh rate of 7.8125s (commercial) or 3.9607s (industrial and
automotive). To ensure all rows of all banks are properly refreshed, 8192 REFRESH com-
mands must be issued every 64ms (commercial) or 32ms (industrial and automotive). The
JEDEC tRFC MAX of 70,000ns is not required as bursting of AUTO REFRESH commands is
allowed.
42. tDELAY is calculated from tIS + tCK + tIH so that CKE registration LOW is guaranteed pri-
or to CK, CK# being removed in a system RESET condition (see Reset (page 125)).
43. tISXR is equal to tIS and is used for CKE setup time during self refresh exit, as shown in
44. tCKE (MIN) of three clocks means CKE must be registered on three consecutive positive
clock edges. CKE must remain at the valid input level the entire time it takes to achieve
the three clocks of registration. Thus, after any CKE transition, CKE may not transition
from its valid level during the time period of tIS + 2 × tCK + tIH.
45. The half-clock of tAOFD’s 2.5 tCK assumes a 50/50 clock duty cycle. This half-clock value
must be derated by the amount of half-clock duty cycle error. For example, if the clock
1Gb: x4, x8, x16 DDR2 SDRAM
AC Timing Operating Specifications
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. S 10/09 EN
41
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT47H128M8HQ-187ELAT:E | 128M X 8 DDR DRAM, 0.35 ns, PBGA60 |
| MT48LC2M32B1TG-7 | 2M X 32 SYNCHRONOUS DRAM, 5.5 ns, PDSO86 |
| MT48LC32M4A2P-7ELIT:G | 32M X 4 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| MT55L256L18FT-12TR | 256K X 18 ZBT SRAM, 9 ns, PQFP100 |
| MT55L256L32FT-12 | 256K X 32 ZBT SRAM, 9 ns, PQFP100 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT47H128M8HV-25AT | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
| MT47H128M8HV-25EAT | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
| MT47H128M8HV-25EIT | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
| MT47H128M8HV-25EL | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
| MT47H128M8HV-25IT | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。