參數(shù)資料
型號(hào)： MT47H128M8HV-187ELIT:E
元件分類： DRAM
英文描述： 128M X 8 DDR DRAM, 0.35 ns, PBGA60
封裝： 8 X 11.50 MM, FBGA-60
文件頁數(shù)： 59/133頁
文件大?。?/td> 9170K
AC Timing Operating Specifications
Table 11: AC Operating Specifications and Conditions
Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table;
VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V
AC Characteristics
-187E
-25E
-25
-3E
-3
-37E
-5E
Units Notes
Parameter
Symbol
Min
Max
Min Max Min Max Min Max Min Max Min Max Min Max
Clock
cycle time
CL = 7 tCK (avg) 1.875
8.0
–
ns
CL = 6 tCK (avg)
2.5
8.0
2.5
8.0
2.5
8.0
–
CL = 5 tCK (avg)
3.0
8.0
2.5
8.0
3.0
8.0
3.0
8.0
3.0
8.0
–
CL = 4 tCK (avg) 3.75
8.0
3.75
8.0
3.75
8.0
3.0
8.0
3.75
8.0
3.75
8.0
5.0
8.0
CL = 3 tCK (avg)
5.0
8.0
5.0
8.0
5.0
8.0
5.0
8.0
5.0
8.0
5.0
8.0
5.0
8.0
CK high-level width tCH (avg) 0.48
0.52
0.48
0.52
0.48
0.52
0.48
0.52
0.48
0.52
0.48
0.52
0.48
0.52
tCK
CK low-level width tCL (avg)
0.48
0.52
0.48
0.52
0.48
0.52
0.48
0.52
0.48
0.52
0.48
0.52
0.48
0.52
tCK
Half clock period
tHP
MIN = lesser of tCH and tCL
MAX = n/a
ps
Absolute tCK
tCK (abs)
MIN = tCK (AVG) MIN + tJITper (MIN)
MAX = tCK (AVG) MAX + tJITper (MAX)
ps
Absolute CK
high-level width
tCH (abs)
MIN = tCK (AVG) MIN × tCH (AVG) MIN + tJITdty (MIN)
MAX = tCK (AVG) MAX × tCH (AVG) MAX + tJITdty (MAX)
ps
Absolute CK
low-level width
tCL (abs)
MIN = tCK (AVG) MIN × tCL (AVG) MIN + tJITdty (MIN)
MAX = tCK (AVG) MAX × tCL (AVG) MAX + tJITdty (MAX)
ps
1Gb:
x4,
x8,
x16
DDR2
SDRAM
AC
Timing
Operating
Specifications
PDF:
09005aef821ae8bf
1GbDDR2.pdf
–
Rev.
S
10/09
EN
31
Micron
Technology,
Inc.
reserves
the
right
to
change
products
or
specifications
without
notice.
2004
Micron
Technology,
Inc.
All
rights
reserved.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT47H128M8HV-25AT 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM
MT47H128M8HV-25EAT 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM
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MT47H128M8HV-25EL 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM
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