- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄224506 > MT47H128M8HV-187ELIT:E 128M X 8 DDR DRAM, 0.35 ns, PBGA60 PDF資料下載
參數(shù)資料
| 型號(hào)： | MT47H128M8HV-187ELIT:E |
| 元件分類： | DRAM |
| 英文描述： | 128M X 8 DDR DRAM, 0.35 ns, PBGA60 |
| 封裝： | 8 X 11.50 MM, FBGA-60 |
| 文件頁(yè)數(shù)： | 121/133頁(yè) |
| 文件大?。?/td> | 9170K |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)當(dāng)前第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)
Notes: 1. Applying power; if CKE is maintained below 0.2 × VDDQ, outputs remain disabled. To
guarantee RTT (ODT resistance) is off, VREF must be valid and a low level must be applied
to the ODT ball (all other inputs may be undefined; I/Os and outputs must be less than
VDDQ during voltage ramp time to avoid DDR2 SDRAM device latch-up). VTT is not ap-
plied directly to the device; however, tVTD should be
≥0 to avoid device latch-up. At
least one of the following two sets of conditions (A or B) must be met to obtain a stable
supply state (stable supply defined as VDD, VDDL, VDDQ, VREF, and VTT are between their
minimum and maximum values as stated in Table 12 (page 42)):
A. Single power source: The VDD voltage ramp from 300mV to VDD,min must take no lon-
ger than 200ms; during the VDD voltage ramp, |VDD - VDDQ| ≤ 0.3V. Once supply voltage
VDD, VDDL, and VDDQ are driven from a single power converter output
VTT is limited to 0.95V MAX
VREF tracks VDDQ/2; VREF must be within ±0.3V with respect to VDDQ/2 during supply
ramp time; does not need to be satisfied when ramping power down
VDDQ ≥ VREF at all times
B. Multiple power sources: VDD ≥ VDDL ≥ VDDQ must be maintained during supply voltage
ramping, for both AC and DC levels, until supply voltage ramping completes (VDDQ
Apply VDD and VDDL before or at the same time as VDDQ; VDD/VDDL voltage ramp time
must be
≤ 200ms from when VDD ramps from 300mV to VDD,min
Apply VDDQ before or at the same time as VTT; the VDDQ voltage ramp time from when
VDD,min is achieved to when VDDQ,min is achieved must be ≤ 500ms; while VDD is ramp-
ing, current can be supplied from VDD through the device to VDDQ
VREF must track VDDQ/2; VREF must be within ±0.3V with respect to VDDQ/2 during sup-
ply ramp time; VDDQ ≥ VREF must be met at all times; does not need to be satisfied
when ramping power down
Apply VTT; the VTT voltage ramp time from when VDDQ,min is achieved to when VTT,min
is achieved must be no greater than 500ms
2. CKE requires LVCMOS input levels prior to state T0 to ensure DQs are High-Z during de-
vice power-up prior to VREF being stable. After state T0, CKE is required to have SSTL_18
input levels. Once CKE transitions to a high level, it must stay HIGH for the duration of
the initialization sequence.
3. For a minimum of 200s after stable power and clock (CK, CK#), apply NOP or DESELECT
commands, then take CKE HIGH.
4. Wait a minimum of 400ns then issue a PRECHARGE ALL command.
5. Issue a LOAD MODE command to the EMR(2). To issue an EMR(2) command, provide
LOW to BA0, and provide HIGH to BA1; set register E7 to “0” or “1” to select appropri-
ate self refresh rate; remaining EMR(2) bits must be “0” (see Extended Mode Register 2
(EMR2) (page 84) for all EMR(2) requirements).
6. Issue a LOAD MODE command to the EMR(3). To issue an EMR(3) command, provide
HIGH to BA0 and BA1; remaining EMR(3) bits must be “0.” Extended Mode Register 3
(EMR3) for all EMR(3) requirements.
7. Issue a LOAD MODE command to the EMR to enable DLL. To issue a DLL ENABLE com-
mand, provide LOW to BA1 and A0; provide HIGH to BA0; bits E7, E8, and E9 can be set
to “0” or “1;” Micron recommends setting them to “0;” remaining EMR bits must be
“0.” Extended Mode Register (EMR) (page 80) for all EMR requirements.
8. Issue a LOAD MODE command to the MR for DLL RESET. 200 cycles of clock input is re-
quired to lock the DLL. To issue a DLL RESET, provide HIGH to A8 and provide LOW to
BA1 and BA0; CKE must be HIGH the entire time the DLL is resetting; remaining MR bits
must be “0.” Mode Register (MR) (page 75) for all MR requirements.
9. Issue PRECHARGE ALL command.
1Gb: x4, x8, x16 DDR2 SDRAM
Initialization
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. S 10/09 EN
88
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT47H128M8HQ-187ELAT:E | 128M X 8 DDR DRAM, 0.35 ns, PBGA60 |
| MT48LC2M32B1TG-7 | 2M X 32 SYNCHRONOUS DRAM, 5.5 ns, PDSO86 |
| MT48LC32M4A2P-7ELIT:G | 32M X 4 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| MT55L256L18FT-12TR | 256K X 18 ZBT SRAM, 9 ns, PQFP100 |
| MT55L256L32FT-12 | 256K X 32 ZBT SRAM, 9 ns, PQFP100 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT47H128M8HV-25AT | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
| MT47H128M8HV-25EAT | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
| MT47H128M8HV-25EIT | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
| MT47H128M8HV-25EL | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
| MT47H128M8HV-25IT | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。