參數(shù)資料
型號: MT47H128M8HV-187ELIT:E
元件分類: DRAM
英文描述: 128M X 8 DDR DRAM, 0.35 ns, PBGA60
封裝: 8 X 11.50 MM, FBGA-60
文件頁數(shù): 18/133頁
文件大?。?/td> 9170K
REFRESH
The commercial temperature DDR2 SDRAM requires REFRESH cycles at an average in-
terval of 7.8125s (MAX) and all rows in all banks must be refreshed at least once every
64ms. The refresh period begins when the REFRESH command is registered and ends
tRFC (MIN) later. The average interval must be reduced to 3.9s (MAX) when TC ex-
ceeds +85°C.
Figure 67: Refresh Mode
CK
CK#
Command
NOP1
PRE
CKE
RA
Address
A10
Bank
Bank(s)3
BA
REF
NOP1
REF2
NOP1
ACT
NOP1
One bank
All banks
tCK
tCH
tCL
RA
DQ4
DM4
DQS, DQS#4
tRFC2
tRP
tRFC (MIN)
T0
T1
T2
T3
T4
Ta0
Tb0
Ta1
Tb1
Tb2
Don’t Care
Indicates a break in
time scale
Notes: 1. NOP commands are shown for ease of illustration; other valid commands may be possi-
ble at these times. CKE must be active during clock positive transitions.
2. The second REFRESH is not required and is only shown as an example of two back-to-
back REFRESH commands.
3.
“Don’t Care” if A10 is HIGH at this point; A10 must be HIGH if more than one bank is
active (must precharge all active banks).
4. DM, DQ, and DQS signals are all “Don’t Care”/High-Z for operations shown.
1Gb: x4, x8, x16 DDR2 SDRAM
REFRESH
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. S 10/09 EN
114
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
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