參數(shù)資料
型號： MT47H128M8HV-187ELIT:E
元件分類： DRAM
英文描述： 128M X 8 DDR DRAM, 0.35 ns, PBGA60
封裝： 8 X 11.50 MM, FBGA-60
文件頁數(shù)： 113/133頁
文件大?。?/td> 9170K
Extended Mode Register (EMR)
The extended mode register controls functions beyond those controlled by the mode
register; these additional functions are DLL enable/disable, output drive strength, on-
die termination (ODT), posted AL, off-chip driver impedance calibration (OCD), DQS#
enable/disable, RDQS/RDQS# enable/disable, and output disable/enable. These func-
tions are controlled via the bits shown in Figure 37. The EMR is programmed via the LM
command and will retain the stored information until it is programmed again or the
device loses power. Reprogramming the EMR will not alter the contents of the memory
array, provided it is performed correctly.
The EMR must be loaded when all banks are idle and no bursts are in progress, and the
controller must wait the specified time tMRD before initiating any subsequent opera-
tion. Violating either of these requirements could result in an unspecified operation.
Figure 37: EMR Definition
DLL
Posted CAS# R
TT
Out
A9
A7 A6 A5 A4 A3
A8
A2 A1 A0
Extended mode
register (Ex)
Address bus
9
7
6
5
4
3
8
2
1
0
A10
A12
BA0
BA1
10
11
12
n
0
14
E1
0
1
Output Drive Strength
Full
Reduced
Posted CAS# Additive Latency (AL)3
0
1
2
3
4
5
6
Reserved
E3
0
1
0
1
0
1
0
1
E4
0
1
0
1
E5
0
1
0
1
DLL Enable
Enable (normal)
Disable (test/debug)
E0
15
E11
0
1
RDQS Enable
No
Yes
OCD Program
An2
ODS
R
TT
DQS#
E10
0
1
DQS# Enable
Enable
Disable
RDQS
R
TT (Nominal)
R
TT disabled
75Ω
150Ω
50Ω
E2
0
1
0
1
E6
0
1
0
1
Outputs
Enabled
Disabled
E12
0
1
0
1
Mode Register Set
Mode register (MR)
Extended mode register (EMR)
Extended mode register (EMR2)
Extended mode register (EMR3)
E15
0
0
1
E14
MRS
BA21
16
0
OCD Operation4
OCD exit
Reserved
Enable OCD defaults
E7
0
1
0
1
E8
0
1
0
1
E9
0
1
Notes: 1. E16 (BA2) is only applicable for densities
≥1Gb, reserved for future use, and must be pro-
grammed to “0.”
2. Mode bits (En) with corresponding address balls (An) greater than E12 (A12) are re-
served for future use and must be programmed to “0.”
3. Not all listed AL options are supported in any individual speed grade.
4. As detailed in the Initialization (page 86) section notes, during initialization of the
OCD operation, all three bits must be set to “1” for the OCD default state, then set to
“0” before initialization is finished.
1Gb: x4, x8, x16 DDR2 SDRAM
Extended Mode Register (EMR)
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. S 10/09 EN
80
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2004 Micron Technology, Inc. All rights reserved.
相關(guān)PDF資料
PDF描述
MT47H128M8HQ-187ELAT:E 128M X 8 DDR DRAM, 0.35 ns, PBGA60
MT48LC2M32B1TG-7 2M X 32 SYNCHRONOUS DRAM, 5.5 ns, PDSO86
MT48LC32M4A2P-7ELIT:G 32M X 4 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
MT55L256L18FT-12TR 256K X 18 ZBT SRAM, 9 ns, PQFP100
MT55L256L32FT-12 256K X 32 ZBT SRAM, 9 ns, PQFP100
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT47H128M8HV-25AT 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM
MT47H128M8HV-25EAT 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM
MT47H128M8HV-25EIT 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM
MT47H128M8HV-25EL 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM
MT47H128M8HV-25IT 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DDR2 SDRAM
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*