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| 型號(hào)： | MT48LC4M16A2P-75:G |
| 元件分類： | DRAM |
| 英文描述： | 4M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封裝： | 0.400 INCH, ROHS COMPLIANT, PLASTIC, TSOP2-54 |
| 文件頁(yè)數(shù)： | 1/72頁(yè) |
| 文件大小： | 3455K |
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Products and specifications discussed herein are subject to change by Micron without notice.
64Mb: x4, x8, x16 SDRAM
Features
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64MSDRAM_1.fm - Rev. N 12/08 EN
1
2000 Micron Technology, Inc. All rights reserved.
Synchronous DRAM
MT48LC16M4A2 – 4 Meg x 4 x 4 banks
MT48LC8M8A2 – 2 Meg x 8 x 4 banks
MT48LC4M16A2 – 1 Meg x 16 x 4 banks
For the latest data sheet, refer to Micron’s Web site: www.micron.com/sdram
Features
PC100- and PC133-compliant
Fully synchronous; all signals registered on positive
edge of system clock
Internal pipelined operation; column address can be
changed every clock cycle
Internal banks for hiding row access/precharge
Programmable burst lengths: 1, 2, 4, 8, or full page
Auto precharge, includes concurrent auto precharge
and auto refresh modes
Self refresh modes: standard and low power
(not available on AT devices)
Refresh
– 64ms, 4,096-cycle refresh (15.6s/row)
(commercial, industrial)
– 16ms, 4,096-cycle refresh (3.9s/row)
(automotive)
LVTTL-compatible inputs and outputs
Single +3.3V ±0.3V power supply
Table 1:
Address Table
16 Meg x 4
8 Meg x 8
4 Meg x 16
Configuration
4 Meg x 4 x
4 banks
2 Meg x 8 x
4 banks
1 Meg x 16 x
4 banks
Refresh count
4K
Row
addressing
4K (A0–A11) 4K (A0–A11) 4K (A0–A11)
Bank
addressing
4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1)
Column
addressing
1K (A0–A9)
512 (A0–A8)
256 (A0–A7)
Notes: 1. Refer to Micron technical note: TN-48-05.
2. Off-center parting line.
3. Contact Micron for product availability.
Part Number Example:
MT48LC8M8A2TG-75:G
Options
Marking
Configurations
– 16 Meg x 4 (4 Meg x 4 x 4 banks)
– 8 Meg x 8 (2 Meg x 8 x 4 banks)
– 4 Meg x 16 (1 Meg x 16 x 4 banks)
16M4
8M8
4M16
Write recovery (tWR)
A2
Plastic package – OCPL2
– 54-pin TSOP II (400 mil)
– 54-pin TSOP II (400 mil) Pb-free,
RoHS-compliant
– 54-ball VFBGA 8mm x 8mm (x16 only)
– 54-ball VFBGA 8mm x 8mm, Pb-free,
RoHS-compliant (x16 only)
TG
P
F4
Timing (cycle time)
– 7.5ns @ CL = 3 (PC133)
– 7.5ns @ CL = 2 (PC133)
– 6ns @ CL = 3 (x16 only)
-75
-7E
-6
Self refresh
– Standard
– Low power
None
L
Operating temperature range
– Commercial (0°C to +70°C)
– Industrial (–40°C to +85°C)
– Automotive (–40°C to +105°C)
None
IT
AT3
Design revision
:G
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT48LC4M16A2P75ITG | 制造商:Micron Technology Inc 功能描述: |
| MT48LC4M16A2P-75ITG | 制造商: 功能描述: |
| MT48LC4M16A2P-7E | 制造商:Micron Technology Inc 功能描述:SDRAM 64MBIT 133MHZ 54TSOP 制造商:Micron Technology Inc 功能描述:SDRAM, 64MBIT, 133MHZ, 54TSOP 制造商:Micron Technology Inc 功能描述:SDRAM, 64MBIT, 133MHZ, 54TSOP, Memory Type:DRAM - Synchronous, Memory Configurat |
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