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參數(shù)資料
| 型號： | MT48LC4M16A2P-75:G |
| 元件分類： | DRAM |
| 英文描述： | 4M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封裝： | 0.400 INCH, ROHS COMPLIANT, PLASTIC, TSOP2-54 |
| 文件頁數(shù)： | 9/72頁 |
| 文件大?。?/td> | 3455K |
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PDF: 09005aef80725c0b/Source: 09005aef806fc13c
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64MSDRAM_2.fm - Rev. N 12/08 EN
17
2000 Micron Technology, Inc. All rights reserved.
64Mb: x4, x8, x16 SDRAM
Functional Description
Reserved states should not be used as unknown operation or incompatibility with future
versions may result.
Figure 7:
CAS Latency
Operating Mode
The normal operating mode is selected by setting M7 and M8 to zero; the other combi-
nations of values for M7 and M8 are reserved for future use and/or test modes. The
programmed burst length applies to both read and write bursts.
Test modes and reserved states should not be used because unknown operation or
incompatibility with future versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via M0–M2 applies to both read and write
bursts; when M9 = 1, the programmed burst length applies to read bursts, but write
accesses are single-location (nonburst) accesses.
Table 6:
CAS Latency
Speed
Allowable Operating Frequency (MHz)
CL = 2
CL = 3
-6
–
≤166
-7E
≤133
≤143
-75
≤100
≤133
CLK
DQ
T2
T1
T3
T0
CL = 3
LZ
DOUT
tOH
t
COMMAND
NOP
READ
tAC
NOP
T4
NOP
DON’T CARE
UNDEFINED
CLK
DQ
T2
T1
T3
T0
CL = 2
LZ
DOUT
tOH
t
COMMAND
NOP
READ
tAC
NOP
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MT48LC4M16A2P75ITG | 制造商:Micron Technology Inc 功能描述: |
| MT48LC4M16A2P-75ITG | 制造商: 功能描述: |
| MT48LC4M16A2P-7E | 制造商:Micron Technology Inc 功能描述:SDRAM 64MBIT 133MHZ 54TSOP 制造商:Micron Technology Inc 功能描述:SDRAM, 64MBIT, 133MHZ, 54TSOP 制造商:Micron Technology Inc 功能描述:SDRAM, 64MBIT, 133MHZ, 54TSOP, Memory Type:DRAM - Synchronous, Memory Configurat |
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