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參數(shù)資料
| 型號(hào)： | MT48LC4M16A2P-75:G |
| 元件分類： | DRAM |
| 英文描述： | 4M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封裝： | 0.400 INCH, ROHS COMPLIANT, PLASTIC, TSOP2-54 |
| 文件頁數(shù)： | 11/72頁 |
| 文件大?。?/td> | 3455K |
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PDF: 09005aef80725c0b/Source: 09005aef806fc13c
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64MSDRAM_2.fm - Rev. N 12/08 EN
19
2000 Micron Technology, Inc. All rights reserved.
64Mb: x4, x8, x16 SDRAM
Commands
LOAD MODE REGISTER
The mode register is loaded via inputs A0–A11. See mode register heading in “Register
Definition” on page 13. The LOAD MODE REGISTER command can only be issued when
all banks are idle, and a subsequent executable command cannot be issued until tMRD
is met.
ACTIVE
The ACTIVE command is used to open (or activate) a row in a particular bank for a
subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address
provided on inputs A0–A11 selects the row. This row remains active (or open) for
accesses until a precharge command is issued to that bank. A precharge command must
be issued before opening a different row in the same bank.
READ
The READ command is used to initiate a burst read access to an active row. The value on
the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–A9 (x4), A0–
A8 (x8), or A0–A7 (x16) selects the starting column location. The value on input A10
determines whether auto precharge is used. If auto precharge is selected, the row being
accessed will be precharged at the end of the read burst; if auto precharge is not selected,
the row will remain open for subsequent accesses. Read data appears on the DQs subject
to the logic level on the DQM inputs two clocks earlier. If a given DQM signal was regis-
tered HIGH, the corresponding DQs will be High-Z two clocks later; if the DQM signal
was registered LOW, the DQs will provide valid data.
WRITE
The WRITE command is used to initiate a burst write access to an active row. The value
on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–A9 (x4),
A0–A8 (x8), or A0–A7 (x16) selects the starting column location. The value on input A10
determines whether auto precharge is used. If auto precharge is selected, the row being
accessed will be precharged at the end of the write burst; if auto precharge is not
selected, the row will remain open for subsequent accesses. Input data appearing on the
DQs is written to the memory array subject to the DQM input logic level appearing coin-
cident with the data. If a given DQM signal is registered LOW, the corresponding data
will be written to memory; if the DQM signal is registered HIGH, the corresponding data
inputs will be ignored, and a write will not be executed to that byte/column location.
PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or
the open row in all banks. The bank(s) will be available for a subsequent row access a
specified time (tRP) after the precharge command is issued. Input A10 determines
whether one or all banks are to be precharged, and in the case where only one bank is to
be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as
“Don’t Care.” After a bank has been precharged, it is in the idle state and must be acti-
vated prior to any READ or WRITE commands being issued to that bank.
Auto Precharge
Auto precharge is a feature that performs the same individual-bank precharge function
described above, without requiring an explicit command. This is accomplished by using
A10 to enable auto precharge in conjunction with a specific READ or WRITE command.
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| MT48LC4M16A2F4-6IT:G | 4M X 16 SYNCHRONOUS DRAM, 5.5 ns, PBGA54 |
| MT46V32M8FG-6TIT:G | 32M X 8 DDR DRAM, 0.7 ns, PBGA60 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT48LC4M16A2P75ITG | 制造商:Micron Technology Inc 功能描述: |
| MT48LC4M16A2P-75ITG | 制造商: 功能描述: |
| MT48LC4M16A2P-7E | 制造商:Micron Technology Inc 功能描述:SDRAM 64MBIT 133MHZ 54TSOP 制造商:Micron Technology Inc 功能描述:SDRAM, 64MBIT, 133MHZ, 54TSOP 制造商:Micron Technology Inc 功能描述:SDRAM, 64MBIT, 133MHZ, 54TSOP, Memory Type:DRAM - Synchronous, Memory Configurat |
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