- 您現在的位置：買賣IC網 > PDF目錄229297 > MT48LC4M16A2P-75:G 4M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 PDF資料下載
參數資料
| 型號： | MT48LC4M16A2P-75:G |
| 元件分類： | DRAM |
| 英文描述： | 4M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封裝： | 0.400 INCH, ROHS COMPLIANT, PLASTIC, TSOP2-54 |
| 文件頁數： | 10/72頁 |
| 文件大小： | 3455K |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁當前第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64MSDRAM_2.fm - Rev. N 12/08 EN
18
2000 Micron Technology, Inc. All rights reserved.
64Mb: x4, x8, x16 SDRAM
Commands
Truth Table 1 provides a quick reference of available commands. This is followed by a
written description of each command. Three additional Truth Tables appear following
“Operation” on page 21; these tables provide current state/next state information.
Notes:
1. A0–A11 define the op-code written to the mode register.
2. A0–A11 provide row address, and BA0, BA1 determine which bank is made active.
3. A0–A9 (x4), A0–A8 (x8), or A0–A7 (x16) provide column address; A10 (HIGH) enables the
auto precharge feature (nonpersistent), while A10 (LOW) disables the auto precharge fea-
ture; BA0, BA1 determine which bank is being read from or written to.
4. A10 (LOW): BA0, BA1 determine the bank being precharged. A10 HIGH: All banks pre-
charged and BA0, BA1 are “Don’t Care.”
5. This command is AUTO REFRESH if CKE is (HIGH), SELF REFRESH if CKE is LOW.
6. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except
for CKE.
7. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock
delay).
COMMAND INHIBIT
The command inhibit function prevents new commands from being executed by the
SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively dese-
lected. Operations already in progress are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM that is
selected (CS# is LOW). This prevents unwanted commands from being registered during
idle or wait states. Operations already in progress are not affected.
Table 7:
Truth Table 1 – Commands and DQM Operation
CKE is HIGH for all commands shown except SELF REFRESH.
Name (Function)
CS#
RAS#
CAS#
WE#
DQM
ADDR
DQs
Notes
COMMAND INHIBIT (NOP)
H
XXXX
X
NO OPERATION (NOP)
L
HHH
X
ACTIVE (Select bank and activate row)
LL
H
X
Bank/row
X
READ
(Select bank and column, and start READ burst)
LHLH
L/H8
Bank/col
X
WRITE
(Select bank and column, and start WRITE burst)
L
H
L
L/H8
Bank/col
Valid
BURST TERMINATE
LH
HL
X
Active
PRECHARGE
(Deactivate row in bank or banks)
LL
H
L
X
Code
X
AUTO REFRESH or SOFT REFRESH
(Enter self refresh mode)
LLL
H
X
LOAD MODE REGISTER
L
LLL
X
Op-code
X
Write enable/output enable
––––L
–
Active
Write inhibit/output High-Z
––––
H
–
High-Z
相關PDF資料 |
PDF描述 |
|---|---|
| M93C06-MB6G | 16 X 16 MICROWIRE BUS SERIAL EEPROM, DSO8 |
| MT48LC4M16A2F4-6IT:G | 4M X 16 SYNCHRONOUS DRAM, 5.5 ns, PBGA54 |
| MT46V32M8FG-6TIT:G | 32M X 8 DDR DRAM, 0.7 ns, PBGA60 |
| MT46V32M8BG-6AT:G | 32M X 8 DDR DRAM, 0.7 ns, PBGA60 |
| M29F800FB55N3E2 | 512K X 16 FLASH 5V PROM, 55 ns, PDSO48 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MT48LC4M16A2P75ITG | 制造商:Micron Technology Inc 功能描述: |
| MT48LC4M16A2P-75ITG | 制造商: 功能描述: |
| MT48LC4M16A2P-7E | 制造商:Micron Technology Inc 功能描述:SDRAM 64MBIT 133MHZ 54TSOP 制造商:Micron Technology Inc 功能描述:SDRAM, 64MBIT, 133MHZ, 54TSOP 制造商:Micron Technology Inc 功能描述:SDRAM, 64MBIT, 133MHZ, 54TSOP, Memory Type:DRAM - Synchronous, Memory Configurat |
發(fā)布緊急采購，3分鐘左右您將得到回復。