參數(shù)資料
型號： MT48LC4M16A2P-75:G
元件分類： DRAM
英文描述： 4M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
封裝： 0.400 INCH, ROHS COMPLIANT, PLASTIC, TSOP2-54
文件頁數(shù)： 31/72頁
文件大小： 3455K
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64MSDRAM_2.fm - Rev. N 12/08 EN
37
2000 Micron Technology, Inc. All rights reserved.
64Mb: x4, x8, x16 SDRAM
Commands
READ with Auto Precharge
Interrupted by a READ (with or without auto precharge): A READ to bank m will inter-
rupt a READ on bank n, CL later. The precharge to bank n will begin when the READ
to bank m is registered (Figure 29 on page 37).
Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will
interrupt a READ on bank n when registered. DQM should be used two clocks prior to
the WRITE command to prevent bus contention. The precharge to bank n will begin
when the WRITE to bank m is registered (Figure 30 on page 38).
WRITE with Auto Precharge
Interrupted by a READ (with or without auto precharge): A READ to bank m will inter-
rupt a WRITE on bank n when registered, with the data-out appearing CL later. The
precharge to bank n will begin after tWR is met, where tWR begins when the READ to
bank m is registered. The last valid WRITE to bank n will be data-in registered one
clock prior to the READ to bank m (Figure 31 on page 38).
Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will
interrupt a WRITE on bank n when registered. The precharge to bank n will begin
after tWR is met, where tWR begins when the WRITE to bank m is registered. The last
valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank
Figure 29:
READ With Auto Precharge Interrupted by a READ
Note:
DQM is LOW.
DON’T CARE
CLK
DQ
DOUT
a
T2
T1
T4
T3
T6
T5
T0
COMMAND
READ - AP
BANK n
NOP
DOUT
a + 1
DOUT
d
DOUT
d + 1
NOP
T7
BANK n
CAS Latency = 3 (BANK m)
BANK m
ADDRESS
Idle
NOP
BANK n,
COL a
BANK m,
COL d
READ - AP
BANK m
Internal
States
t
Page Active
READ with Burst of 4
Interrupt Burst, Precharge
Page Active
READ with Burst of 4
Precharge
RP - BANK n
tRP - BANK m
CAS Latency = 3 (BANK n)
TRANSITIONING DATA
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT48LC4M16A2P75ITG 制造商:Micron Technology Inc 功能描述:
MT48LC4M16A2P-75ITG 制造商: 功能描述:
MT48LC4M16A2P-7E 制造商:Micron Technology Inc 功能描述:SDRAM 64MBIT 133MHZ 54TSOP 制造商:Micron Technology Inc 功能描述:SDRAM, 64MBIT, 133MHZ, 54TSOP 制造商:Micron Technology Inc 功能描述:SDRAM, 64MBIT, 133MHZ, 54TSOP, Memory Type:DRAM - Synchronous, Memory Configurat
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