- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄229297 > MT48LC4M16A2P-75:G 4M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 PDF資料下載
參數(shù)資料
| 型號： | MT48LC4M16A2P-75:G |
| 元件分類： | DRAM |
| 英文描述： | 4M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封裝： | 0.400 INCH, ROHS COMPLIANT, PLASTIC, TSOP2-54 |
| 文件頁數(shù)： | 27/72頁 |
| 文件大?。?/td> | 3455K |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁當(dāng)前第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64MSDRAM_2.fm - Rev. N 12/08 EN
33
2000 Micron Technology, Inc. All rights reserved.
64Mb: x4, x8, x16 SDRAM
Commands
Figure 23:
WRITE-to-PRECHARGE
Note:
DQM could remain LOW in this example if the WRITE burst is a fixed length of two.
Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE
command. When truncating a WRITE burst, the input data applied coincident with the
BURST TERMINATE command will be ignored. The last data written (provided that
DQM is LOW at that time) will be the input data applied one clock previous to the
BURST TERMINATE command. This is shown in Figure 24 on page 34, where data n is
the last desired data element of a longer burst.
PRECHARGE
The PRECHARGE command (Figure 25 on page 34) is used to deactivate the open row in
a particular bank or the open row in all banks. The bank(s) will be available for a subse-
quent row access some specified time (tRP) after the PRECHARGE command is issued.
Input A10 determines whether one or all banks are to be precharged, and in the case
where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all
banks are to be precharged, inputs BA0, BA1 are treated as “Don’t Care.” After a bank has
been precharged, it is in the idle state and must be activated prior to any READ or WRITE
commands being issued to that bank.
DON’T CARE
DQM
CLK
DQ
T2
T1
T4
T3
T0
COMMAND
ADDRESS
BANK a,
COL n
T5
NOP
WRITE
PRECHARGE
NOP
DIN
n
DIN
n + 1
ACTIVE
t RP
BANK
(a or all)
t WR
BANK a,
ROW
DQM
DQ
COMMAND
ADDRESS
BANK a,
COL n
NOP
WRITE
PRECHARGE
NOP
DIN
n
DIN
n + 1
ACTIVE
t RP
BANK
(a or all)
t WR
BANK a,
ROW
T6
NOP
tWR @ tCLK ≥ 15ns
tWR = tCLK < 15ns
TRANSITIONING DATA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M93C06-MB6G | 16 X 16 MICROWIRE BUS SERIAL EEPROM, DSO8 |
| MT48LC4M16A2F4-6IT:G | 4M X 16 SYNCHRONOUS DRAM, 5.5 ns, PBGA54 |
| MT46V32M8FG-6TIT:G | 32M X 8 DDR DRAM, 0.7 ns, PBGA60 |
| MT46V32M8BG-6AT:G | 32M X 8 DDR DRAM, 0.7 ns, PBGA60 |
| M29F800FB55N3E2 | 512K X 16 FLASH 5V PROM, 55 ns, PDSO48 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT48LC4M16A2P75ITG | 制造商:Micron Technology Inc 功能描述: |
| MT48LC4M16A2P-75ITG | 制造商: 功能描述: |
| MT48LC4M16A2P-7E | 制造商:Micron Technology Inc 功能描述:SDRAM 64MBIT 133MHZ 54TSOP 制造商:Micron Technology Inc 功能描述:SDRAM, 64MBIT, 133MHZ, 54TSOP 制造商:Micron Technology Inc 功能描述:SDRAM, 64MBIT, 133MHZ, 54TSOP, Memory Type:DRAM - Synchronous, Memory Configurat |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。