參數(shù)資料
型號： PCI6515ZHK
廠商： Texas Instruments, Inc.
英文描述： SINGLE SOCKET CARDBUS CONTROLLER WITH DEDICATED SMART CARD SOCKET
中文描述： 單插槽CardBus控制器，專用智能卡插槽
文件頁數(shù)： 121/148頁
文件大?。?/td> 760K
代理商： PCI6515ZHK
65
Table 64.
Socket Present State Register Description (Continued)
BIT
SIGNAL
TYPE
FUNCTION
9
BADVCCREQ
R
Bad VCC request. This bit indicates that the host software has requested that the socket be powered at
an invalid voltage.
0 = Normal operation (default)
1 = Invalid VCC request by host software
Data lost. This bit indicates that a PC Card removal event may have caused lost data because the cycle
did not terminate properly or because write data still resides in the PCI6515 controller.
0 = Normal operation (default)
1 = Potential data loss due to card removal
Not a card. This bit indicates that an unrecognizable PC Card has been inserted in the socket. This bit is
not updated until a valid PC Card is inserted into the socket.
0 = Normal operation (default)
1 = Unrecognizable PC Card detected
READY(IREQ)//CINT. This bit indicates the current status of the READY(IREQ)//CINT signal at the PC
Card interface.
0 = READY(IREQ)//CINT is low.
1 = READY(IREQ)//CINT is high.
CardBus card detected. This bit indicates that a CardBus PC Card is inserted in the socket. This bit is not
updated until another card interrogation sequence occurs (card insertion).
16-bit card detected. This bit indicates that a 16-bit PC Card is inserted in the socket. This bit is not
updated until another card interrogation sequence occurs (card insertion).
Power cycle. This bit indicates the status of each card powering request. This bit is encoded as:
0 = Socket is powered down (default).
1 = Socket is powered up.
CCD2. This bit reflects the current status of the CCD2 signal at the PC Card interface. Changes to this
signal during card interrogation are not reflected here.
0 = CCD2 is low (PC Card may be present)
1 = CCD2 is high (PC Card not present)
CCD1. This bit reflects the current status of the CCD1 signal at the PC Card interface. Changes to this
signal during card interrogation are not reflected here.
0 = CCD1 is low (PC Card may be present).
1 = CCD1 is high (PC Card not present).
CSTSCHG. This bit reflects the current status of the CSTSCHG signal at the PC Card interface.
0 = CSTSCHG is low.
1 = CSTSCHG is high.
One or more bits in the register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not
enabled, then these bits are cleared by the assertion of PRST or GRST.
8
DATALOST
R
7
NOTACARD
R
6
IREQCINT
R
5
CBCARD
R
4
16BITCARD
R
3
PWRCYCLE
R
2
CDETECT2
R
1
CDETECT1
R
0
CARDSTS
R
6.4
Socket Force Event Register
This register is used to force changes to the socket event register (offset 00h, see Section 6.1) and the socket present
state register (offset 08h, see Section 6.3). The CVSTEST bit (bit 14) in this register must be written when forcing
changes that require card interrogation. See Table 65 for a complete description of the register contents.
Bit
Name
Type
Default
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Socket force event
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bit
Name
Type
Default
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Socket force event
W
X
R
X
W
X
W
X
W
X
W
X
W
X
W
X
W
X
R
X
W
X
W
X
W
X
W
X
W
X
W
X
Register:
Offset:
Type:
Default:
Socket force event
CardBus Socket Address + 0Ch
Read-only, Write-only
0000 XXXXh
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