參數(shù)資料
型號： PCI6515ZHK
廠商： Texas Instruments, Inc.
英文描述： SINGLE SOCKET CARDBUS CONTROLLER WITH DEDICATED SMART CARD SOCKET
中文描述： 單插槽CardBus控制器，專用智能卡插槽
文件頁數(shù)： 144/148頁
文件大?。?/td> 760K
代理商： PCI6515ZHK
84
8.4
PCI Clock/Reset Timing Requirements Over Recommended Ranges of Supply
Voltage and Operating Free-Air Temperature
PARAMETER
ALTERNATE
SYMBOL
TEST CONDITIONS
MIN
MAX
UNIT
tc
tw(H)
tw(L)
tr, tf
tw
tsu
Cycle time, PCLK
tcyc
thigh
tlow
v/
t
trst
trst-clk
30
ns
Pulse duration (width), PCLK high
11
ns
Pulse duration (width), PCLK low
11
ns
Slew rate, PCLK
1
4
V/ns
Pulse duration (width), GRST
1
ms
Setup time, PCLK active at end of PRST
100
s
8.5
PCI Timing Requirements Over Recommended Ranges of Supply Voltage and
Operating Free-Air Temperature
This data manual uses the following conventions to describe time ( t ) intervals. The format is t
A
, where
subscript A
indicates the type of dynamic parameter being represented. One of the following is used: t
pd
= propagation delay time,
t
d
(t
en
, t
dis
) = delay time, t
su
= setup time, and t
h
= hold time.
PARAMETER
ALTERNATE
SYMBOL
TEST CONDITIONS
MIN
MAX
UNIT
tpd
Propagation delay time, See Note 4
PCLK-to-shared signal
valid delay time
tval
CL = 50 pF,
See Note 4
11
ns
PCLK-to-shared signal
invalid delay time
tinv
2
ten
tdis
tsu
th
NOTE 4: PCI shared signals are AD31AD0, C/BE3C/BE0, FRAME, TRDY, IRDY, STOP, IDSEL, DEVSEL, and PAR.
Enable time, high impedance-to-active delay time from PCLK
ton
toff
tsu
th
2
ns
Disable time, active-to-high impedance delay time from PCLK
28
ns
Setup time before PCLK valid
7
ns
Hold time after PCLK high
0
ns
8.6
Smart Card Timing Specifications Over Recommended Operating Conditions
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tsc_clk
trst1
tio1
tATR1
trst2
tio2
tATR2
tdeact
NOTE 5: If the ICC does not initiate the ATR within the reception window, then the PCI6515 must initiate a contact deactivation within 50 ms.
SC_CLK clock period
200
250
1000
ns
Cold reset SC_RST time
40000
45000
tsc_clk
tsc_clk
tsc_clk
tsc_clk
tsc_clk
tsc_clk
ms
Cold reset SC_I/O high-impedance transition time
200
Cold reset ATR reception window, see Note 5
380
42000
Warm reset SC_RST time
40000
45000
Warm reset SC_I/O high-impedance transition time
200
Warm reset ATR reception window, see Note 5
380
42000
Contact deactivation time
100
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