參數(shù)資料
型號： PCI6515ZHK
廠商： Texas Instruments, Inc.
英文描述： SINGLE SOCKET CARDBUS CONTROLLER WITH DEDICATED SMART CARD SOCKET
中文描述： 單插槽CardBus控制器，專用智能卡插槽
文件頁數(shù)： 130/148頁
文件大?。?/td> 760K
代理商： PCI6515ZHK
76
7.7
Header Type and BIST Register
The header type and built-in self-test (BIST) register indicates the Smart Card controller PCI header type and no
built-in self-test. See Table 76 for a complete description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Header type and BIST
Type
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
x
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Header type and BIST
0Eh
Read-only
00x0h
Table 76. Header Type and BIST Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
158
BIST
R
Built-in self-test. The Smart Card controller does not include a BIST; therefore, this field returns 00h
when read.
70
HEADER_TYPE
R
PCI header type. The Smart Card controller includes the standard PCI header. Bit 7 indicates if the Smart
Card is a multifunction device.
7.8
Smart Card Base Address Register
The Smart Card base address register specifies the base address of the memory-mapped interface registers. Since
the implementation of the Smart Card controller core in the PCI6515 controller contains 2 sockets, the size of the base
address register is 4096 bytes. See Table 77 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Smart Card base address
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Smart Card base address
Type
RW
RW
RW
RW
RW
R
R
R
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Smart Card base address
10h
Read/Write, Read-only
0000 0000h
Table 77. Smart Card Base Address Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
3113
BAR
RW
Base address. This field specifies the upper bits of the 32-bit starting base address.
124
RSVD
R
Reserved. Bits 124 return 0s when read to indicate that the size of the base address is 8192 bytes.
3
PREFETCHABLE
R
Prefetchable. Since this base address is not prefetchable, bit 3 returns 0 when read.
21
RSVD
R
Reserved. Bits 21 return 0s when read.
0
MEM_INDICATOR
R
Memory space indicator. Bit 0 is hardwired to 0 to indicate that the base address maps into memory
space.
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