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3.4.4
Function 0 (CardBus) Subsystem Identification
The subsystem vendor ID register (PCI offset 40h, see Section 4.26) and subsystem ID register (PCI offset 42h, see
Section 4.27) make up a doubleword of PCI configuration space for function 0. This doubleword register is used for
system and option card (mobile dock) identification purposes and is required by some operating systems.
Implementation of this unique identifier register is a
PC 99/PC 2001
requirement.
The PCI6515 controller offers two mechanisms to load a read-only value into the subsystem registers. The first
mechanism relies upon the system BIOS providing the subsystem ID value. The default access mode to the
subsystem registers is read-only, but can be made read/write by clearing bit 5 (SUBSYSRW) in the system control
register (PCI offset 80h, see Section 4.29). Once this bit is cleared, the BIOS can write a subsystem identification
value into the registers at PCI offset 40h. The BIOS must set the SUBSYSRW bit such that the subsystem vendor
ID register and subsystem ID register are limited to read-only access. This approach saves the added cost of
implementing the serial electrically erasable programmable ROM (EEPROM).
In some conditions, such as in a docking environment, the subsystem vendor ID register and subsystem ID register
must be loaded with a unique identifier via a serial EEPROM. The PCI6515 controller loads the data from the serial
EEPROM after a reset of the primary bus. Note that the SUSPEND input gates the PCI reset from the entire PCI6515
core, including the serial-bus state machine (see Section 3.8.5,
Suspend Mode
, for details on using SUSPEND).
The PCI6515 controller provides a two-line serial-bus host controller that can interface to a serial EEPROM. See
Section 3.6,
Serial EEPROM Interface
,
for details on the two-wire serial-bus controller and applications.
3.4.5
Function 5 (Smart Card) Subsystem Identification
The subsystem identification register is used for system and option card identification purposes. This register can
be initialized from the serial EEPROM or programmed via the subsystem access register at offset 50h in the PCI
configuration space (see Section 7.22,
Subsystem Access Register
). See Table 715 for a complete description of
the register contents.
The contents of the subsystem access register are aliased to the subsystem vendor ID and subsystem ID registers
at Function 5 PCI offsets 2Ch and 2Eh, respectively. See Table 715 for a complete description of the register
contents.
3.5
PC Card Applications
The PCI6515 controller supports all the PC Card features and applications as described below.
Card insertion/removal and recognition per the
PC Card Standard
(release 8.1)
Speaker and audio applications
LED socket activity indicators
PC Card controller programming model
CardBus socket registers
3.5.1
PC Card Insertion/Removal and Recognition
The
PC Card Standard
(release 8.1) addresses the card-detection and recognition process through an interrogation
procedure that the socket must initiate on card insertion into a cold, nonpowered socket. Through this interrogation,
card voltage requirements and interface (16-bit versus CardBus) are determined.
The scheme uses the card-detect and voltage-sense signals. The configuration of these four terminals identifies the
card type and voltage requirements of the PC Card interface.