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| 型號(hào)： | PCI6515ZHK |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | SINGLE SOCKET CARDBUS CONTROLLER WITH DEDICATED SMART CARD SOCKET |
| 中文描述： | 單插槽CardBus控制器，專(zhuān)用智能卡插槽 |
| 文件頁(yè)數(shù)： | 50/148頁(yè) |
| 文件大小： | 760K |
| 代理商： | PCI6515ZHK |
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316
PCI6515
PIC
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6
IRQ3
IRQ4
IRQ5
IRQ15
IRQ9
IRQ10
Figure 311. IRQ Implementation
Power-on software is responsible for programming the multifunction routing status register to reflect the IRQ
configuration of a system implementing the PCI6515 controller. The multifunction routing status register is a global
register that is shared between the four PCI6515 functions. See Section 4.35,
Multifunction Routing Status Register
,
for details on configuring the multifunction terminals.
The parallel ISA-type IRQ signaling from the MFUNC6MFUNC0 terminals is compatible with the input signal
requirements of the 8259 PIC. The parallel IRQ option is provided for system designs that require legacy ISA IRQs.
Design constraints may demand more MFUNC6MFUNC0 IRQ terminals than the PCI6515 controller makes
available.
3.7.4
Using Parallel PCI Interrupts
Parallel PCI interrupts are available when exclusively in parallel PCI interrupt/parallel ISA IRQ signaling mode, and
when only IRQs are serialized with the IRQSER protocol. The INTA, INTB, INTC, and INTD can be routed to MFUNC
terminals (MFUNC0, MFUNC1, MFUNC2, and MFUNC4). If bit 29 (INTRTIE) is set in the system control register (PCI
offset 80h, see Section 4.29), then INTA and INTB are tied internally. When the TIEALL bit is set, all four functions
return a value of 01h on reads from the interrupt pin register for both parallel and serial PCI interrupts.
The INTRTIE and TIEALL bits affect the read-only value provided through accesses to the interrupt pin register (PCI
offset 3Dh, see Section 4.24). Table 311 summarizes the interrupt signaling modes.
Table 311. Interrupt Pin Register Cross Reference
INTRTIE Bit
TIEALL Bit
INTPIN
Function 0 (CardBus)
INTPIN
Function 5 (Smart Card)
0
0
0x01 (INTA)
Determined by bits 65 (INT_SEL field) in Smart Card
general control register (see Section 7.21)
1
0
0x01 (INTA)
X
1
0x01 (INTA)
0x01 (INTA)
3.7.5
Using Serialized IRQSER Interrupts
The serialized interrupt protocol implemented in the PCI6515 controller uses a single terminal to communicate all
interrupt status information to the host controller. The protocol defines a serial packet consisting of a start cycle,
multiple interrupt indication cycles, and a stop cycle. All data in the packet is synchronous with the PCI clock. The
packet data describes 16 parallel ISA IRQ signals and the optional 4 PCI interrupts INTA, INTB, INTC, and INTD. For
details on the IRQSER protocol, refer to the document
Serialized IRQ Support for PCI Systems
.
3.7.6
SMI Support in the PCI6515 Controller
The PCI6515 controller provides a mechanism for interrupting the system when power changes have been made to
the PC Card socket interfaces. The interrupt mechanism is designed to fit into a system maintenance interrupt (SMI)
scheme. SMI interrupts are generated by the PCI6515 controller, when enabled, after a write cycle to the socket
control register (CB offset 10h, see Section 6.5) of the CardBus register set, or the ExCA power control register (ExCA
offset 02h/802h, see Section 5.3) causes a power cycle change sequence to be sent on the power switch interface.
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