參數(shù)資料
型號： PCI6515ZHK
廠商： Texas Instruments, Inc.
英文描述： SINGLE SOCKET CARDBUS CONTROLLER WITH DEDICATED SMART CARD SOCKET
中文描述： 單插槽CardBus控制器，專用智能卡插槽
文件頁數(shù)： 82/148頁
文件大?。?/td> 760K
代理商： PCI6515ZHK
424
4.35 Multifunction Routing Status Register
The multifunction routing status register is used to configure the MFUNC6MFUNC0 terminals. These terminals may
be configured for various functions. This register is intended to be programmed once at power-on initialization. The
default value for this register can also be loaded through a serial EEPROM. See Table 414 for a complete description
of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Multifunction routing status
Type
R
RW
RW
RW
R
RW
RW
RW
R
RW
RW
RW
R
RW
RW
RW
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Multifunction routing status
Type
R
RW
RW
RW
R
RW
RW
RW
R
RW
RW
RW
R
RW
RW
RW
Default
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Multifunction routing status
8Ch
Read/Write, Read-only
0000 1000h
Table 414. Multifunction Routing Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
3128
RSVD
R
Bits 3128 return 0s when read.
2724
MFUNC6
RW
Multifunction terminal 6 configuration. These bits control the internal signal mapped to the MFUNC6 terminal
as follows:
0000 = RSVD
0100 = IRQ4
1000 = IRQ8
0001 = CLKRUN
0101 = IRQ5
1001 = IRQ9
0010 = IRQ2
0110 = IRQ6
1010 = IRQ10
0011 = IRQ3
0111 = IRQ7
1011 = IRQ11
1100 = IRQ12
1101 = IRQ13
1110 = IRQ14
1111 = IRQ15
2320
MFUNC5
RW
Multifunction terminal 5 configuration. These bits control the internal signal mapped to the MFUNC5 terminal
as follows:
0000 = GPI4
0100 = SC_DBG_RX
0001 = GPO4
0101 = IRQ5
0010 = RSVD
0110 = RSVD
0011 = IRQ3
0111 = RSVD
1000 = CAUDPWM
1001 = IRQ9
1010 = RSVD
1011 = OHCI_LED
1100 = LEDA1
1101 = LED_SKT
1110 = GPE
1111 = IRQ15
1916
MFUNC4
RW
Multifunction terminal 4 configuration. These bits control the internal signal mapped to the MFUNC4 terminal
as follows:
0000 = GPI3
0100 = IRQ4
0001 = GPO3
0101 = SC_DBG_TX
0010 = LOCK PCI
0110 = RSVD
0011 = IRQ3
0111 = RSVD
1000 = CAUDPWM
1001 = IRQ9
1010 = INTD
1011 = RSVD
1100 = RI_OUT
1101 = LED_SKT
1110 = GPE
1111 = IRQ15
1512
MFUNC3
RW
Multifunction terminal 3 configuration. These bits control the internal signal mapped to the MFUNC3 terminal
as follows:
0000 = RSVD
0100 = IRQ4
1000 = IRQ8
0001 = IRQSER
0101 = IRQ5
1001 = IRQ9
0010 = IRQ2
0110 = IRQ6
1010 = IRQ10
0011 = IRQ3
0111 = IRQ7
1011 = IRQ11
1100 = IRQ12
1101 = IRQ13
1110 = IRQ14
1111 = IRQ15
118
MFUNC2
RW
Multifunction terminal 2 configuration. These bits control the internal signal mapped to the MFUNC2 terminal
as follows:
0000 = GPI2
0100 = IRQ4
1000 = CAUDPWM
0001 = GPO2
0101 = IRQ5
1001 = RSVD
0010 = RSVD
0110 = RSVD
1010 = IRQ10
0011 = IRQ3
0111 = RSVD
1011 = INTC
1100 = RI_OUT
1101 = TEST_MUX
1110 = GPE
1111 = IRQ7
One or more bits in this register are cleared only by the assertion of GRST.
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