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參數(shù)資料
| 型號(hào)： | PCI6515ZHK |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | SINGLE SOCKET CARDBUS CONTROLLER WITH DEDICATED SMART CARD SOCKET |
| 中文描述： | 單插槽CardBus控制器，專(zhuān)用智能卡插槽 |
| 文件頁(yè)數(shù)： | 62/148頁(yè) |
| 文件大小： | 760K |
| 代理商： | PCI6515ZHK |
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44
Table 43. Command Register Description
BIT
SIGNAL
TYPE
FUNCTION
1511
RSVD
R
Reserved. Bits 1511 return 0s when read.
10
INT_DISABLE
RW
INTx disable. When set to 1, this bit disables the function from asserting interrupts on the INTx signals.
0 = INTx assertion is enabled (default)
1 = INTx assertion is disabled
9
FBB_EN
R
Fast back-to-back enable. The PCI6515 controller does not generate fast back-to-back transactions;
therefore, this bit is read-only. This bit returns a 0 when read.
8
SERR_EN
RW
System error (SERR) enable. This bit controls the enable for the SERR driver on the PCI interface. SERR
can be asserted after detecting an address parity error on the PCI bus. Both this bit and bit 6 must be set
for the PCI6515 controller to report address parity errors.
0 = Disables the SERR output driver (default)
1 = Enables the SERR output driver
7
RSVD
R
Reserved. Bit 7 returns 0 when read.
6
PERR_EN
RW
Parity error response enable. This bit controls the PCI6515 response to parity errors through the PERR
signal. Data parity errors are indicated by asserting PERR, while address parity errors are indicated by
asserting SERR.
0 = PCI6515 controller ignores detected parity errors (default).
1 = PCI6515 controller responds to detected parity errors.
5
VGA_EN
RW
VGA palette snoop. When set to 1, palette snooping is enabled (i.e., the PCI6515 controller does not
respond to palette register writes and snoops the data). When the bit is 0, the PCI6515 controller treats
all palette accesses like all other accesses.
4
MWI_EN
R
Memory write-and-invalidate enable. This bit controls whether a PCI initiator device can generate memory
write-and-invalidate commands. The PCI6515 controller does not support memory write-and-invalidate
commands, it uses memory write commands instead; therefore, this bit is hardwired to 0. This bit returns
0 when read. Writes to this bit have no effect.
3
SPECIAL
R
Special cycles. This bit controls whether or not a PCI device ignores PCI special cycles. The PCI6515
controller does not respond to special cycle operations; therefore, this bit is hardwired to 0. This bit returns
0 when read. Writes to this bit have no effect.
2
MAST_EN
RW
Bus master control. This bit controls whether or not the PCI6515 controller can act as a PCI bus initiator
(master). The PCI6515 controller can take control of the PCI bus only when this bit is set.
0 = Disables the PCI6515 ability to generate PCI bus accesses (default)
1 = Enables the PCI6515 ability to generate PCI bus accesses
1
MEM_EN
RW
Memory space enable. This bit controls whether or not the PCI6515 controller can claim cycles in PCI
memory space.
0 = Disables the PCI6515 response to memory space accesses (default)
1 = Enables the PCI6515 response to memory space accesses
0
IO_EN
RW
I/O space control. This bit controls whether or not the PCI6515 controller can claim cycles in PCI I/O space.
0 = Disables the PCI6515 controller from responding to I/O space accesses (default)
1 = Enables the PCI6515 controller to respond to I/O space accesses
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| PCI6520 | 制造商:PLX 制造商全稱(chēng):PLX 功能描述:Transparent FastLane⑩ PCI-X -to- PCI-X Bridge |
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| PCI6520-CB13BI G | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI PCIX to PCIX Bridge 64Bit 133MHz RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PCI6520-XX13BC | 制造商:PLX 制造商全稱(chēng):PLX 功能描述:Transparent FastLane⑩ PCI-X -to- PCI-X Bridge |
| PCI6540 | 制造商:PLX 制造商全稱(chēng):PLX 功能描述:Dual-Mode (Transparent & Non-Transparent) Universal FastLane⑩ PCI-X -to- PCI-X Bridge |
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