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| 型號(hào)： | PCI6515ZHK |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | SINGLE SOCKET CARDBUS CONTROLLER WITH DEDICATED SMART CARD SOCKET |
| 中文描述： | 單插槽CardBus控制器，專(zhuān)用智能卡插槽 |
| 文件頁(yè)數(shù)： | 55/148頁(yè) |
| 文件大小： | 760K |
| 代理商： | PCI6515ZHK |
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321
D3
hot
Low-power state. Transition state before D3
cold
D3
cold
PME signal-generation capable. Main power is removed and VAUX is available.
D3
off
No power and completely nonfunctional
NOTE 1: In the D0-uninitialized state, the PCI6515 controller does not generate PME and/or interrupts. When bits 0 (IO_EN) and 1 (MEM_EN)
of the command register (PCI offset 04h, see Section 4.4) are both set, the PCI6515 controller switches the state to D0-active. Transition
from D3cold to the D0-uninitialized state happens at the deassertion of PRST. The assertion of GRST forces the controller to the
D0-uninitialized state immediately.
NOTE 2: The PWR_STATE bits (bits 10) of the power-management control/status register (PCI offset A4h, see Section 4.43) only code for four
power states, D0, D1, D2, and D3hot. The differences between the three D3 states is invisible to the software because the controller
is not accessible in the D3cold or D3off state.
Similarly, bus power states of the PCI bus are B0B3. The bus power states B0B3 are derived from the device power
state of the originating bridge device.
For the operating system (OS) to manage the controller power states on the PCI bus, the PCI function must support
four power-management operations. These operations are:
Capabilities reporting
Power status reporting
Setting the power state
System wake-up
The OS identifies the capabilities of the PCI function by traversing the new capabilities list. The presence of
capabilities in addition to the standard PCI capabilities is indicated by a 1 in bit 4 (CAPLIST) of the status register (PCI
offset 06h, see Section 4.5).
The capabilities pointer provides access to the first item in the linked list of capabilities. For the PCI6515 controller,
a CardBus bridge with PCI configuration space header type 2, the capabilities pointer is mapped to an offset of 14h.
The first byte of each capability register block is required to be a unique ID of that capability. PCI power management
has been assigned an ID of 01h. The next byte is a pointer to the next pointer item in the list of capabilities. If there
are no more items in the list, then the next item pointer must be set to 0. The registers following the next item pointer
are specific to the capability of the function. The PCI power-management capability implements the register block
outlined in Table 314.
Table 314. Power-Management Registers
REGISTER NAME
OFFSET
Power-management capabilities
Next item pointer
Capability ID
A0h
Data
Power-management control/status register bridge support extensions
Power-management control/status (CSR)
A4h
The power-management capabilities register (PCI offset A2h, see Section 4.42) provides information on the
capabilities of the function related to power management. The power-management control/status register (PCI offset
A4h, see Section 4.43) enables control of power-management states and enables/monitors power-management
events. The data register is an optional register that can provide dynamic data.
For more information on PCI power management, see the
PCI Bus Power Management Interface Specification for
PCI to CardBus Bridges
.
3.8.8.2 Smart Card (Function 5) Power Management
The
PCI Bus Power Management Interface Specification
is applicable for the Smart Card dedicated sockets. This
function supports the D0 and D3 power states.
Table 315. Function 5 Power-Management Registers
REGISTER NAME
OFFSET
Power-management capabilities
Next item pointer
Capability ID
44h
Data
Power-management control/status register bridge support extensions
Power-management control/status (CSR)
48h
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