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RELEASED
PM73122 AAL1GATOR-32
DATASHEET
PMC-1981419
ISSUE 7
32 LINK CES/DBCES AAL1 SAR PROCESSOR
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
339
13.7 Interrupt and Status Registers
These registers indicate the current status of the device and any conditions
that might require processor attention.
Table 35 Interrupt and Status Registers Memory Map
Address
Register Description
Register Mnemonic
0x81000
Master Interrupt Register
MSTR_INTR_REG
0x81010
A1SP0 Interrupt Register
A1SP0_INTR_REG
0x81011
A1SP1 Interrupt Register
A1SP1_INTR_REG
0x81012
A1SP2 Interrupt Register
A1SP2_INTR_REG
0x81013
A1SP2 Interrupt Register
A1SP3_INTR_REG
0x81020
A1SP0 Status Register
A1SP0_STAT_REG
0x81021
A1SP1 Status Register
A1SP1_STAT_REG
0x81022
A1SP2 Status Register
A1SP2_STAT_REG
0x81023
A1SP3 Status Register
A1SP3_STAT_REG
0x81030
A1SP0 Transmit Idle State FIFO
A1SP0_TIDLE_FIFO
0x81031
A1SP1 Transmit Idle State FIFO
A1SP1_TIDLE_FIFO
0x81032
A1SP2 Transmit Idle State FIFO
A1SP2_TIDLE_FIFO
0x81033
A1SP3 Transmit Idle State FIFO
A1SP3_TIDLE_FIFO
0x81040
A1SP0 Receive Status FIFO
A1SP0_RSTAT_FIFO
0x81041
A1SP1 Receive Status FIFO
A1SP1_RSTAT_FIFO
0x81042
A1SP2 Receive Status FIFO
A1SP2_RSTAT_FIFO
0x81043
A1SP3 Receive Status FIFO
A1SP3_RSTAT_FIFO
0x81100
Master Interrupt Enable Register
MSTR_INTR_REG
0x81110
A1SP0 Interrupt Enable Register
A1SP0_INTR_EN
0x81111
A1SP1 Interrupt Enable Register
A1SP1_INTR_EN
0x81112
A1SP2 Interrupt Enable Register
A1SP2_INTR_EN
0x81113
A1SP2 Interrupt Enable Register
A1SP3_INTR_EN
0x81140
A1SP0 Receive Status FIFO Enable Register
A1SP0_RSTAT_EN
0x81141
A1SP1 Receive Status FIFO Enable Register
A1SP1_RSTAT_EN
0x81142
A1SP2 Receive Status FIFO Enable Register
A1SP2_RSTAT_EN