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RELEASED
PM73122 AAL1GATOR-32
DATASHEET
PMC-1981419
ISSUE 7
32 LINK CES/DBCES AAL1 SAR PROCESSOR
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
342
A1SP1_INTR
When set, there is an interrupt pending from the A1SP1 block. Read the
A1SP1_INTR_REG to determine the cause of the interrupt. This bit indicates
current status and will clear only when no interrupt conditions remain in
A1SP1_INTR_REG.On read:
0) No interrupt pending from the A1SP1 block
1) Interrupt pending from the A1SP1 block
A1SP2_INTR
When set, there is an interrupt pending from the A1SP2 block. Read the
A1SP2_INTR_REG to determine the cause of the interrupt. This bit indicates
current status and will clear only when no interrupt conditions remain in
A1SP2_INTR_REG.On read:
0) No interrupt pending from the A1SP2 block
1) Interrupt pending from the A1SP2 block
A1SP3_INTR
When set, there is an interrupt pending from the A1SP3 block. Read the
A1SP3_INTR_REG to determine the cause of the interrupt. This bit indicates
current status and will clear only when no interrupt conditions remain in
A1SP3_INTR_REG.On read:
0) No interrupt pending from the A1SP3 block
1) Interrupt pending from the A1SP3 block
RAM1_PAR_ERR
When set, indicates there was a parity error encountered in the RAM1
interface. This bit is cleared on read. On read:
0) No parity error encountered in RAM1 interface
1) Parity error encountered in RAM1 interface
RAM2_PAR_ERR
When set, indicates there was a parity error encountered in the RAM2
interface. This bit is cleared on read. On read:
0) No parity error encountered in RAM2 interface
1) Parity error encountered in RAM2 interface