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RELEASED
PM73122 AAL1GATOR-32
DATASHEET
PMC-1981419
ISSUE 7
32 LINK CES/DBCES AAL1 SAR PROCESSOR
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
42
Pin Name
Type
Pin
No.
Function
DV5
Input
T2
Active High Drop Bus Payload Indicator
(DV5).
This active high signal locates the
position of the floating payloads for each
tributary within the SBI BUS structure. Timing
differences between the port timing and the SBI
BUS timing are indicated by adjustments of this
payload pointer relative to the fixed SBI BUS
structure.
Multiple PHY devices can drive this signal at
uniquely assigned tributary columns within the
SBI BUS structure. All movements indicated by
this signal must be accompanied by appropriate
adjustments in the DPL signal.
DV5 is sampled on the rising edge of REFCLK.
ADATA[7]
ADATA[6]
ADATA[5]
ADATA[4]
ADATA[3]
ADATA[2]
ADATA[1]
ADATA[0]
Output
G2
H3
H1
K3
J1
P3
R2
U1
Add Data (ADATA[7:0]).
The Add data bus is a
time division multiplexed bus which transports
tributaries by assigning them to fixed octets
within the SBI BUS structure.
The AAL1gator-32 drives ADATA[7:0] only at
uniquely assigned tributary columns within the
SBI BUS structure.
ADATA[7:0] is asserted on the rising edge of
REFCLK.
Maximum output current (IMAX) = 8 mA
ADP
Output
T4
Add Bus Data Parity (ADP).
This signal carries
the even or odd parity for the add bus signals.
The parity calculation encompasses
ADATA[7:0], APL and AV5 signals.
The selection of even or odd parity is made via
SBI_PAR_CTL bit of Insert Control Register
The AAL1gator drives ADP only at uniquely
assigned tributary columns within the SBI BUS
structure.
ADP is asserted on the rising edge of REFCLK.
Maximum output current (IMAX) = 8 mA