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RELEASED
PM73122 AAL1GATOR-32
DATASHEET
PMC-1981419
ISSUE 7
32 LINK CES/DBCES AAL1 SAR PROCESSOR
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
27
Pin Name
Type
Pin
No.
Function
ALE
Input
AD12
The address latch enable signal (ALE) latches
the A[19:0] signals during the address phase of
a bus transaction. When ALE is set high, the
address latches are transparent. When ALE is
set low, the address latches hold the address
provided on A[19:0].
ALE has an internal pull-up resistor.
WRB
Input
AF11
The write strobe signal (WRB) qualifies write
accesses to the AAL1gator-32 device. When
CSB is set low, the D[15:0] bus contents are
clocked into the addressed register on the rising
edge of WRB.
Note that if CSB, WRB and RDB are all low, all
chip outputs are tristated. Therefore WRB and
RDB should never be active at the same time
during functional operation.
RDB
Input
AC12
The read strobe signal (RDB) qualifies read
accesses to the AAL1gator-32 device. When
CSB is set low, the AAL1gator-32 device drives
the D[15:0] bus with the contents of the
addressed register on the falling edge of RDB.
Note that if CSB, WRB and RDB are all low, all
chip outputs are tristated. Therefore WRB and
RDB should never be active at the same time
during functional operation.
CSB
Input
AE11
The chip select signal (CSB) qualifies read/write
accesses to the AAL1gator-32 device. The
CSB signal must be set low during read and
write accesses. When CSB is set high, the
microprocessor interface signals are ignored by
the AAL1gator-32 device.
If CSB is not required (register accesses
controlled only by WRB and RDB) then CSB
should be connected to an inverted version of
the RSTB signal.
Note that if CSB, WRB and RDB are all low, all
chip outputs are tristated.