參數(shù)資料
型號： S71PL191HB0BFI100
廠商： SPANSION LLC
元件分類： 存儲器
英文描述： SPECIALTY MEMORY CIRCUIT, PBGA73
封裝： 9 X 13 MM, LEAD FREE, FBGA-73
文件頁數(shù)： 158/172頁
文件大?。?/td> 4662K
代理商： S71PL191HB0BFI100
70
S29PL127H/S29PL129H
S29PL127H_129H_00A1 May 7, 2004
Pr el i m i n ary
AC CHARACTERISTICS
Erase and Program Operations
Notes:
1. Not 100% tested.
2. See the “Flash Erase And Programming Performance” section for more information.
Parameter
All Speeds
JEDEC
Std
Description
Unit
tAVAV
tWC
Write Cycle Time (Note 1)
Min
70
ns
tAVWL
tAS
Address Setup Time
Min
0
ns
tASO
Address Setup Time to OE# low during toggle bit polling
Min
15
ns
tWLAX
tAH
Address Hold Time
Min
35
ns
tAHT
Address Hold Time From CE1#f or OE# high
during toggle bit polling
Min
0
ns
tDVWH
tDS
Data Setup Time
Min
30
ns
tWHDX
tDH
Data Hold Time
Min
0
ns
tOEPH
Output Enable High during toggle bit polling
Min
10
ns
tGHWL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
tWLEL
tWS
WE# Setup Time (CE1# to WE#)
Min
0
ns
tELWL
tCS
CE1# Setup Time
Min
0
ns
tEHWH
tWH
WE# Hold Time (CE1# to WE#)
Min
0
ns
tWHEH
tCH
CE1# Hold Time
Min
0
ns
tWLWH
tWP
Write Pulse Width
Min
40
ns
tWHDL
tWPH
Write Pulse Width High
Min
25
ns
tSR/W
Latency Between Read and Write Operations
Min
0
ns
tWHWH1
Programming Operation (Note 2)
Word
Typ
6
s
tWHWH1
Accelerated Programming Operation,
Word or Byte (Note 2)
Typ
4
s
tWHWH2
tWHWH2 Sector Erase Operation (Note 2)
Typ
0.5
sec
tVCS
VCC Setup Time (Note 1)
Min
50
s
tRB
Write Recovery Time from RY/BY#
Min
0
ns
tBUSY
Program/Erase Valid to RY/BY# Delay
Max
90
ns
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