參數(shù)資料
型號： S71PL191HB0BFI100
廠商： SPANSION LLC
元件分類： 存儲器
英文描述： SPECIALTY MEMORY CIRCUIT, PBGA73
封裝： 9 X 13 MM, LEAD FREE, FBGA-73
文件頁數(shù)： 83/172頁
文件大?。?/td> 4662K
代理商： S71PL191HB0BFI100
2
S29PL127H/S29PL129H
S29PL127H_129H_00A1 May 7, 2004
Pr el i m i n ary
General Description
The S29PL127H/S29PL129H is a 128 Mbit, 3.0 volt-only Page Mode and Simul-
taneous Read/Write Flash memory device organized as 8 Mwords. The device is
offered in various multi-chip packages. The word-wide data (x16) appears on
DQ15-DQ0. This device can be programmed in-system or in standard EPROM
programmers. A 12.0 V VPP is not required for write or erase operations.
The device offers fast page access times of 30 ns, with corresponding random
access times of 70 ns allowing high speed microprocessors to operate without
wait states. To eliminate bus contention the device has separate chip enable
(CE#), write enable (WE#) and output enable (OE#) controls. Simultaneous
Read/Write Operation with Zero Latency. Dual Chip Enables allow access to two
64 Mbit partitions of the 128 Mbit memory space (S29PL129H only).
The Simultaneous Read/Write architecture provides simultaneous operation
by dividing the memory space into 4 banks, which can be considered to be four
separate memory arrays as far as certain operations are concerned. The device
can improve overall system performance by allowing a host system to program
or erase in one bank, then immediately and simultaneously read from another
bank with zero latency (with two simultaneous operations operating at any one
time). This releases the system from waiting for the completion of a program or
erase operation, greatly improving system performance.
The device can be organized in both top and bottom sector configurations. The
banks are organized as follows:
Page Mode Features
The page size is 8 words. After initial page access is accomplished, the page
mode operation provides fast read access speed of random locations within that
page.
Standard Flash Memory Features
The device requires a single 3.0 volt power supply (2.7 V to 3.6 V) for both
read and write functions. Internally generated and regulated voltages are pro-
vided for the program and erase operations.
The device is entirely command set compatible with the JEDEC 42.4 single-
power-supply Flash standard. Commands are written to the command reg-
ister using standard microprocessor write timing. Register contents serve as in-
puts to an internal state-machine that controls the erase and programming
circuitry. Write cycles also internally latch addresses and data needed for the
programming and erase operations. Reading data out of the device is similar to
reading from other Flash or EPROM devices.
Chip Enable Configuration (S29PL127H)
Bank
Sectors
A
16 Mbit (4 Kw x 8 and 32 Kw x 31)
B
48 Mbit (32 Kw x 96)
C
48 Mbit (32 Kw x 96)
D
16 Mbit (4 Kw x 8 and 32 Kw x 31)
Chip Enable Configuration (S29PL129H)
CE1# Control
CE2# Control
Bank 1A
16 Mbit (4 Kw x 8 and 32 Kw x 31)
Bank 2A
48 Mbit (32 Kw x 96)
Bank 1B
48 Mbit (32 Kw x 96)
Bank 2B
16 Mbit (4 Kw x 8 and 32 Kw x 31)
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