參數(shù)資料
型號： S71PL191HB0BFI100
廠商： SPANSION LLC
元件分類： 存儲器
英文描述： SPECIALTY MEMORY CIRCUIT, PBGA73
封裝： 9 X 13 MM, LEAD FREE, FBGA-73
文件頁數(shù)： 75/172頁
文件大?。?/td> 4662K
代理商： S71PL191HB0BFI100
72
64 Mb pSRAM (Supplier 1)
S71PL191_193Hx0_00A1 March 10, 2004
Adva nce
Inform at i o n
Notes:
1. AC measurements are assumed tR, tF = 5 ns.
2. Parameters tOD, tODO, tBD and tODW define the time at which the output goes the open condition and are not output
voltage reference levels.
3. Data cannot be retained at deep power-down stand-by mode.
4. If OE# is high during the write cycle, the outputs will remain at high impedance.
5. During the output state of I/O signals, input signals of reverse polarity must not be applied.
6. If CE1# or LB#/UB# goes LOW coincident with or after WE# goes LOW, the outputs will remain at high impedance.
7. If CE1# or LB#/UB# goes HIGH coincident with or before WE# goes HIGH, the outputs will remain at high
impedance.
tAA
Page Mode Address Access Time
–
30
ns
tAOH
Page Mode Output Data Hold Time
10
–
ns
tWC
Write Cycle Time
70
10000
ns
tWP
Write Pulse Width
50
–
ns
tCW
Chip Enable to End of Write
70
–
ns
tBW
Data Byte Control to End of Write
60
–
ns
tAW
Address Valid to End of Write
60
–
ns
tAS
Address Set-up Time
0
–
ns
tWR
Write Recovery Time
0
–
ns
tCEH
Chip Enable High Pulse Width
10
–
ns
tWEH
Write Enable High Pulse Width
6
–
ns
tODW
WE# Low to Output High-Z
–
20
ns
tOEW
WE# High to Output Active
0
–
ns
tDS
Data Set-up Time
30
–
ns
tDH
Data Hold Time
0
–
ns
tCS
CE2 Set-up Time
0
–
ns
tCH
CE2 Hold Time
300
–
s
tDPD
CE2 Pulse Width
10
–
ms
tCHC
CE2 Hold from CE1#
0
–
ns
tCHP
CE2 Hold from Power On
30
–
s
Table 14. AC Test Conditions
Parameter
Condition
Output load
30 pF + 1 TTL Gate
Input pulse level
VDD 0.2 V, 0.2 V
Timing measurements
VDD × 0.5
Reference level
VDD× 0.5
tR, tF
5 ns
Table 13. AC Characteristics and Operating Conditions (TA = -25°C to 85°C, VDD = 2.6 to 3.3V) (Continued)
Symbol
Parameter
Min
Max
Unit
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