參數(shù)資料
型號(hào)： S71PL191HB0BFI100
廠商： SPANSION LLC
元件分類： 存儲(chǔ)器
英文描述： SPECIALTY MEMORY CIRCUIT, PBGA73
封裝： 9 X 13 MM, LEAD FREE, FBGA-73
文件頁數(shù)： 62/172頁
文件大?。?/td> 4662K
代理商： S71PL191HB0BFI100
58
S29JL064H
S29JL064HA1 May 7, 2004
Pr el i m i n ary
Erase And Programming Performance
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 100,000 cycles; checkerboard data
pattern.
2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See
Table 4 for further information on command definitions.
6. The device has a minimum cycling endurance of 100,000 cycles per sector.
7. Contact the local sales office for minimum cycling endurance values in specific applications and operating conditions.
Parameter
Unit
Comments
Sector Erase Time
0.4
5
sec
Excludes 00h programming
prior to erasure (Note 4)
Chip Erase Time
56
sec
Word Program Time
7
210
s
Excludes system level
overhead (Note 5)
Accelerated Byte/Word Program Time
4
120
s
Accelerated Chip Programming Time
10
30
sec
Byte Program Time
5
150
s
Chip Program Time
Byte Mode
42
126
sec
Word Mode
28
84
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