參數(shù)資料
型號: S71PL191HB0BFI100
廠商: SPANSION LLC
元件分類: 存儲器
英文描述: SPECIALTY MEMORY CIRCUIT, PBGA73
封裝: 9 X 13 MM, LEAD FREE, FBGA-73
文件頁數(shù): 70/172頁
文件大?。?/td> 4662K
代理商: S71PL191HB0BFI100
66
32 Mb pSRAM (Supplier 2)
S71PL191_193Hx0_00A1 March 10, 2004
Adva nce
Inform at i o n
Write Cycle Notes
1. A write occurs during the overlap(tWP) of low CS# and low WE#. A write begins when CS# goes low and WE# goes
low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte
operation. A write ends at the earliest transition when CS# goes high and WE# goes high. The tWP is measured
from the beginning of write to the end of write.
2. tCW is measured from the CS# going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CSE# or WE#
going high.
Figure 33. Timing Waveform of Write Cycle (Note2)(CS# Controlled,
ZZ#=VIH)
Figure 34. Timing Waveform of Write Cycle (Note3)(UB#, LB# Controlled,
ZZ#=VIH)
tAS(3)
Address
Data Valid
Data in
Data out
High-Z
tWC
tCW(2)
tAW
tBW
tWP(1)
tDH
tDW
tWR(4)
CS#
UB#, LB#
WE#
Address
Data Valid
Data in
Data out
High-Z
tWC
tCW(2)
tBW
tWP(1)
tDH
tDW
tWR(4)
tAW
tAS(3)
CS#
UB#, LB#
WE#
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