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| 型號(hào)： | SC2200UFH-233 |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | 微處理器 |
| 英文描述： | Thin Client On a Chip |
| 中文描述： | 瘦客戶機(jī)片上 |
| 文件頁(yè)數(shù)： | 172/433頁(yè) |
| 文件大小： | 3255K |
| 代理商： | SC2200UFH-233 |
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172
Revision 3.0
G
Core Logic Module
(Continued)
3 Volt Suspend
The Core Logic module supports the stopping of the CPU
and system clocks for a 3V Suspend state. If appropriately
configured, via the Clock Stop Control register (F0 Index
BCh), the Core Logic module asserts internal SUSP_3V
after it has gone through the SUSP#/SUSPA# handshake.
SUSP_3V is a state indicator, indicating that the system is
in a low-activity state and Suspend Modulation is active.
This indicator can be used to put the system into a low-
power state (the system clock can be turned off).
Internal SUSP_3V is connected to the enable control of the
clock generators, so that the clocks to the CPU and the
Core Logic module (and most other system devices) are
stopped. The Core Logic module continues to decrement
all of its device timers and respond to external SMI inter-
rupts after the input clock has been stopped, as long as the
32 KHz clock continues to oscillate. Any SMI event or
unmasked interrupt causes the Core Logic module to deas-
sert SUSP_3V, restarting the system clocks. As the CPU or
other device might include a PLL, the Core Logic module
holds SUSP# active for a pre-programmed period of delay
(the PLL re-sync delay) that varies from 0 to 15 ms. After
this period has expired, the Core Logic module deasserts
SUSP#, stopping Suspend. SMI# is held active for the
entire period, so that the CPU reenters SMM when the
clocks are restarted.
Save-to-Disk
Save-to-Disk is supported by the Core Logic module. In
this state, the power is typically removed from the Core
Logic module and from the entire SC2200, causing the
state of the legacy peripheral devices to be lost. Shadow
registers are provided for devices which allow their state to
be saved prior to removing power. This is necessary
because the legacy AT peripheral devices used several
write only registers. To restore the exact state of these
devices on resume, the write only register values are
“shadowed” so that the values can be saved by the power
management software.
The PC/AT compatible keyboard controller (KBC) and
floppy port (FDC) do not exist in the SC2200. However, it is
possible that one is attached on the ISA bus or the LPC
bus (e.g., in a SuperI/O device). Some of the KBC and FDC
registers are shadowed because they cannot be safely
read. Additional shadow registers for other functions are
described in Table 5-29 "F0: PCI Header and Bridge Con-
figuration Registers for GPIO and LPC Support" on page
199.
5.2.10.3 Peripheral Power Management
The Core Logic module provides peripheral power man-
agement using a combination of device idle timers, address
traps, and general purpose I/O pins. Idle timers are used in
conjunction with traps to support powering down peripheral
devices.
Device Idle Timers and Traps
Idle timers are used to power manage a peripheral by
determining when the peripheral has been inactive for a
specified period of time, and removing power from the
peripheral at the end of that time period.
Idle timers are provided for the commonly-used peripherals
(FDC, IDE, Parallel/Serial Ports, and Mouse/Keyboard). In
addition, there are three user-defined timers that can be
configured for either I/O or memory ranges.
The idle timers are 16-bit countdown timers with a one sec-
ond time base, providing a timeout range of 1 to 65536
seconds (1092 minutes) (18 hours).
When the idle timer count registers are loaded with a non-
zero value and enabled, the timers decrement until one of
two possibilities happens: a bus cycle occurs at that I/O or
memory range, or the timer decrements to zero.
If a bus cycle occurs, the timer is reloaded and begins dec-
rementing again. If the timer decrements to zero, and
power management is enabled (F0 Index 80h[0] = 1), the
timer generates an SMI.
When an idle timer generates an SMI, the SMI handler
manages the peripheral power, disables the timer, and
enables the trap. The next time an event occurs, the trap
generates an SMI. This time, the SMI handler applies
power to the peripheral, resets the timer, and disables the
trap.
Relevant registers for controlling Device Idle Timers are: F0
Index 80h, 81h, 82h, 93h, 98h-9Eh, and ACh.
Relevant registers for controlling User Defined Device Idle
Timers are: F0 Index 81h, 82h, A0h, A2h, A4h, C0h, C4h,
C8h, CCh, CDh, and CEh.
Although not considered as device idle timers, two addi-
tional timers are provided by the Core Logic module. The
Video Idle Timer used for Suspend-determination and the
VGA Timer used for SoftVGA.
The programming bits for these timers are:
F0 Index 81h[7], Video Access Idle Timer Enable
F0 Index 82h[7], Video Access Trap Enable
F0 Index A6h[15:0], Video Timer Count
F0 Index 83h[3], VGA Timer Enable
F0 Index 8Bh[6], VGA Timer Base
F0 Index 8Eh[7:0], VGA Timer Count
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