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Revision 3.0
G
Core Logic Module
(Continued)
Index 8Ch
IRQ Speedup Timer Count Register (R/W)
Reset Value: 00h
7:0
IRQ Speedup Timer Load Value.
This field represents the load value for the IRQ speedup timer. It is loaded into the
counter when Suspend Modulation is enabled (F0 Index 96h[0] = 1) and an INTR or an access to I/O Port 061h occurs.
When the event occurs, the Suspend Modulation logic is inhibited, permitting full performance operation of the GX1 module.
Upon expiration, no SMI is generated; the Suspend Modulation begins again. The IRQ speedup timer’s timebase is 1 msec.
This speedup mechanism allows instantaneous response to system interrupts for full-speed interrupt processing. A typical
value here would be 2 to 4 msec.
Index 8Dh
Video Speedup Timer Count Register (R/W)
Reset Value: 00h
7:0
Video Speedup Timer Load Value.
This field represents the load value for the Video speedup timer. It is loaded into the
counter when Suspend Modulation is enabled (F0 Index 96[0] = 1) and any access to the graphics controller occurs. When
a video access occurs, the Suspend Modulation logic is inhibited, permitting full-performance operation of the GX1 module.
Upon expiration, no SMI is generated, and Suspend Modulation begins again. The video speedup timer’s timebase is 1
msec.
This speedup mechanism allows instantaneous response to video activity for full speed during video processing calcula-
tions. A typical value here would be 50 msec to 100 msec.
Index 8Eh
VGA Timer Count Register (R/W)
Reset Value: 00h
7:0
VGA Timer Load Value.
This field represents the load value for VGA Timer. It is loaded into the counter when the timer is
enabled (F0 Index 83h[3] = 1). The counter is decremented with each clock of the configured timebase (F0 Index 8Bh[6]).
Upon expiration of the counter, an SMI is generated and the status is reported at F1BAR0+I/O Offset 00h/02h[6] (only).
Once expired, this counter must be re-initialized by either disabling and enabling it, or by writing a new count value in this
register.
Note:
Although grouped with the power management Idle Timers, the VGA Timer is not a power management function.
It is not affected by the Global Power Management Enable setting at F0 Index 80h[0].
Index 8Fh-92h
Reserved
Reset Value: 00h
Index 93h
Miscellaneous Device Control Register (R/W)
Reset Value: 00h
7
Floppy Drive Port Select.
Indicates whether all system resources used to power manage the floppy drive use the primary,
or secondary FDC addresses for decode.
0: Secondary.
1: Primary.
Reserved.
Must be set to 1.
Partial Primary Hard Disk Decode.
This bit is used to restrict the addresses which are decoded as primary hard disk
accesses.
0: Power management monitors all reads and writes to I/O Port 1F0h-1F7h, 3F6h-3F7h (excludes writes to 3F7h), and
170h-177h, 376h-377h (excludes writes to 377h).
1: Power management monitors only writes to I/O Port 1F6h and 1F7h.
Partial Secondary Hard Disk Decode.
This bit is used to restrict the addresses which are decoded as secondary hard disk
accesses.
0: Power management monitors all reads and writes to I/O Port 170h-177h, 376h-377h (excludes writes to 377h).
1: Power management monitors only writes to I/O Port 176h and 177h.
Reserved.
Must be set to 0.
Mouse on Serial Enable.
Mouse is present on a Serial Port.
0: No.
1: Yes.
If a mouse is attached to a serial port (i.e., this bit is set to 1), that port is removed from the serial device list being used to
monitor serial port access for power management purposes and added to the keyboard/mouse decode. This is done
because a mouse, along with the keyboard, is considered an input device and is used only to determine when to blank the
screen.
This bit and bit 0 of this register determine the decode used for the Keyboard/Mouse Idle Timer Count Register (F0 Index
9Eh) as well as the Parallel/Serial Port Idle Timer Count Register (F0 Index 9Ch).
Mouse Port Select.
Selects which serial port the mouse is attached to:
0: COM1
1: COM2.
For more information see the description of bit 1 in this register (above).
6
5
4
3:2
1
0
Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)
Bit
Description