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G
Signal Definitions
(Continued)
AH8
VPD4
I
IN
T
V
IO
---
AH9
VPD0
I
IN
T
V
IO
---
AH10
V
SS
GND
---
---
---
AH11
V
CORE
PWR
---
---
---
AH12
V
SS
GND
---
---
---
AH13
V
CORE
PWR
---
---
---
AH14
V
SS
GND
---
---
---
AH15
V
CORE
PWR
---
---
---
AH16
SDCLK1
O
O
2/5
V
IO
---
AH17
V
CORE
PWR
---
---
---
AH18
V
SS
GND
---
---
---
AH19
V
CORE
PWR
---
---
---
AH20
V
SS
GND
---
---
---
AH21
V
CORE
PWR
---
---
---
AH22
V
SS
GND
---
---
---
AH23
4
MD28
I/O
IN
T
,
TS
2/5
V
IO
---
AH24
4
MD55
I/O
IN
T
,
TS
2/5
V
IO
---
AH25
4
MD51
I/O
IN
T
,
TS
2/5
V
IO
---
AH26
4
MD48
I/O
IN
T
,
TS
2/5
V
IO
---
AH27
4
MD23
I/O
IN
T
,
TS
2/5
V
IO
---
AH28
SDCLK_OUT
O
O
2/5
V
IO
---
AH29
MA12
O
O
2/5
V
IO
---
AH30
4
MD11
I/O
IN
T
,
TS
2/5
V
IO
---
AH31
4
MD10
I/O
IN
T
,
TS
2/5
V
IO
---
AJ1
GPIO10
I/O
(PU
22.5
)
IN
TS
,
O
8/8
V
IO
PMR[18] = 0 and
PMR[8] = 0
DSR2#
I
(PU
22.5
)
IN
TS
PMR[18] = 1 and
PMR[8] = 0
IDE_IORDY1
I
(PU
22.5
)
IN
TS1
PMR[18] = 0 and
PMR[8] = 1
SDTEST1
O
(PU
22.5
)
O
2/5
PMR[18] = 1 and
PMR[8] = 1
AJ2
GPIO8
I/O
(PU
22.5
)
IN
TS
,
O
8/8
V
IO
PMR[17] = 0 and
PMR[8] = 0
CTS2#
I
(PU
22.5
)
IN
TS
PMR[17] = 1 and
PMR[8] = 0
IDE_DREQ1
I
(PU
22.5
)
IN
TS1
PMR[17] = 0 and
PMR[8] = 1
SDTEST4
O
(PU
22.5
)
O
2/5
PMR[17] = 1 and
PMR[8] = 1
AJ3
V
IO
PWR
---
---
---
AJ4
SIN2
I
IN
TS
V
IO
PMR[28] = 0
SDTEST3
O
O
2/5
PMR[28] = 1
AJ5
TMS
I
(PU
22.5
)
IN
PCI
V
IO
---
AJ6
VPD7
I
IN
T
V
IO
---
Ball
No.
Signal Name
I/O
(PU/PD)
Buffer
1
Type
Power
Rail
Configuration
AJ7
VPD6
I
IN
T
V
IO
---
AJ8
VPD2
I
IN
T
V
IO
---
AJ9
GPIO38/IRRX2
I/O
(PU
22.5
)
IN
PCI
,
O
PCI
V
IO
PMR[14]
6
= 0 and
PMR[22]
6
= 0. The
IRRX2 input is con-
nected to the input
path of GPIO38.
There is no logic
required to enable
IRRX2, just a sim-
ple connection.
Hence, when
GPIO38 is the
selected function,
IRRX2 is also
selected.
LPCPD#
O
O
PCI
PMR[14]
6
= 1 and
PMR[22]
6
= 1
AJ10
GPIO35
I/O
(PU
22.5
)
IN
PCI
,
O
PCI
V
IO
PMR[14]
6
= 0 and
PMR[22]
6
= 0
LAD3
I/O
(PU
22.5
)
IN
PCI
,
O
PCI
PMR[14]
6
= 1 and
PMR[22]
6
= 1
AJ11
GPIO32
I/O
(PU
22.5
)
IN
PCI
,
O
PCI
V
IO
PMR[14]
6
= 0 and
PMR[22]
6
= 0
LAD0
I/O
(PU
22.5
)
IN
PCI
,
O
PCI
PMR[14]
6
= 1 and
PMR[22]
6
= 1
AJ12
GPIO12
I/O
(PU
22.5
)
IN
AB
,
O
8/8
V
IO
PMR[19] = 0
AB2C
I/O
(PU
22.5
)
IN
AB
,
OD
8
PMR[19] = 1
AJ13
AB1C
I/O
(PU
22.5
)
IN
AB
,
OD
8
V
IO
PMR[23]
3
= 0
GPIO20
I/O
(PU
22.5
)
IN
T
,
O
3/5
PMR[23]
3
= 1 and
PMR[7] = 0
DOCCS#
O
O3/5
PMR[23]
3
= 1 and
PMR[7] = 1
AJ14
AC97_CLK
O
O
2/5
V
IO
PMR[25] = 1
AJ15
AC97_RST#
O
O
2/5
V
IO
FPCI_MON = 0
F_STOP#
O
O
2/5
FPCI_MON = 1
AJ16
SDCLK3
O
O
2/5
V
IO
---
AJ17
4
MD56
I/O
IN
T
,
TS
2/5
V
IO
---
AJ18
4
MD58
I/O
IN
T
,
TS
2/5
V
IO
---
AJ19
4
MD61
I/O
IN
T
,
TS
2/5
V
IO
---
AJ20
DQM7
O
O
2/5
V
IO
---
AJ21
DQM3
O
O
2/5
V
IO
---
AJ22
4
MD25
I/O
IN
T
,
TS
2/5
V
IO
---
AJ23
4
MD29
I/O
IN
T
,
TS
2/5
V
IO
---
AJ24
4
MD54
I/O
IN
T
,
TS
2/5
V
IO
---
AJ25
4
MD50
I/O
IN
T
,
TS
2/5
V
IO
---
AJ26
DQM6
O
O
2/5
V
IO
---
Ball
No.
Signal Name
I/O
(PU/PD)
Buffer
1
Type
Power
Rail
Configuration
Table 2-2.
432-EBGA Ball Assignment - Sorted by Ball Number (Continued)