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24
Revision 3.0
G
Signal Definitions
(Continued)
C20
2
IDE_DATA9
I/O
IN
TS1
,
TS
1/4
V
IO
PMR[24] = 0
DDC_SDA
I/O
IN
T
,
OD
4
PMR[24] = 1
C21
IDE_IOR0#
O
O
1/4
V
IO
PMR[24] = 0
TFTD10
O
O
1/4
PMR[24] = 1
C22
IDE_DATA6
I/O
IN
TS1
,
TS
1/4
V
IO
PMR[24] = 0
IRQ9
I
IN
TS1
PMR[24] = 1
C23
IDE_DATA3
I/O
IN
TS1
,
TS
1/4
V
IO
PMR[24] = 0
TFTD12
O
O
1/4
PMR[24] = 1
C24
IDE_DREQ0
I
IN
TS1
V
IO
PMR[24] = 0
TFTD8
O
O
1/4
PMR[24] = 1
C25
IDE_DACK0#
O
O
1/4
V
IO
PMR[24] = 0
TFTD0
O
O
1/4
PMR[24] = 1
C26
IDE_ADDR1
O
O
1/4
V
IO
PMR[24] = 0
TFTD2
O
O
1/4
PMR[24] = 1
C27
OVER_CUR#
I
IN
TS
V
IO
---
C28
PLL6B
I/O
IN
TS
,
TS
2/5
V
IO
PMR[29] = 0
TEST1
O
O
2/5
PMR[29] = 1
C29
V
IO
PWR
---
---
---
C30
X32I
I
WIRE
V
BAT
---
C31
V
PLL3
PWR
---
---
---
D1
PCIRST#
O
O
PCI
V
IO
---
D2
GNT1#
O
O
PCI
V
IO
---
DID1
I
(PD
100
)
IN
STRP
Strap (See Table 2-
6 on page 51.)
D3
PCICLK0
O
O
PCI
V
IO
---
FPCI_MON
I
(PD
100
)
IN
STRP
Strap (See Table 2-
6 on page 51.)
D4
GNT0#
O
O
PCI
V
IO
---
DID0
I
(PD
100
)
IN
STRP
Strap (See Table 2-
6 on page 51.)
D5
AD25
I/O
IN
PCI
,
O
PCI
V
IO
Cycle Multiplexed
D1
I/O
IN
PCI
,
O
PCI
D6
AD20
I/O
IN
PCI
,
O
PCI
V
IO
Cycle Multiplexed
A20
O
O
PCI
D7
AD18
I/O
IN
PCI
,
O
PCI
V
IO
Cycle Multiplexed
A18
O
O
PCI
D8
C/BE2#
I/O
(PU
22.5
)
IN
PCI
,
O
PCI
V
IO
Cycle Multiplexed
D10
I/O
(PU
22.5
)
IN
PCI
,
O
PCI
Ball
No.
Signal Name
I/O
(PU/PD)
Buffer
1
Type
Power
Rail
Configuration
D9
STOP#
I/O
(PU
22.5
)
IN
PCI
,
O
PCI
V
IO
Cycle Multiplexed
D15
I/O
(PU
22.5
)
IN
PCI
,
O
PCI
D10
V
SS
GND
---
---
---
D11
V
CORE
PWR
---
---
---
D12
V
SS
GND
---
---
---
D13
V
CORE
PWR
---
---
---
D14
V
SS
GND
---
---
---
D15
V
CORE
PWR
---
---
---
D16
AD1
I/O
IN
PCI
,
O
PCI
V
IO
Cycle Multiplexed
A1
O
O
PCI
D17
V
CORE
PWR
---
---
---
D18
V
SS
GND
---
---
---
D19
V
CORE
PWR
---
---
---
D20
V
SS
GND
---
---
---
D21
V
CORE
PWR
---
---
---
D22
V
SS
GND
---
---
---
D23
IDE_DATA2
I/O
TS1
,
TS
1/4
V
IO
PMR[24] = 0
TFTD14
O
O
1/4
PMR[24] = 1
D24
IDE_IOW0#
O
O
1/4
V
IO
PMR[24] = 0
TFTD9
O
O
1/4
PMR[24] = 1
D25
IRQ14
I
IN
TS1
V
IO
PMR[24] = 0
TFTD1
O
O
1/4
PMR[24] = 1
D26
SIN1
I
IN
TS
V
IO
---
D27
X27O
O
WIRE
V
IO
---
D28
PLL2B
I/O
IN
T
,
TS
2/5
V
IO
PMR[29] = 0
TEST0
O
O
2/5
PMR[29] = 1
D29
X32O
O
WIRE
V
BAT
---
D30
V
BAT
PWR
---
---
---
D31
LED#
O
OD
14
V
SB
---
E1
FRAME#
I/O
(PU
22.5
)
IN
PCI
,
O
PCI
V
IO
---
E2
PCICLK
I
IN
T
V
IO
---
E3
REQ1#
I
(PU
22.5
)
IN
PCI
V
IO
---
E4
PCICLK1
O
O
PCI
V
IO
---
LPC_ROM
I
(PD
100)
IN
STRP
Strap (See Table 2-
6 on page 51.)
E28
AV
SSPLL3
GND
---
---
---
E29
PWRBTN#
I
(PU
100)
IN
BTN
V
SB
---
E30
4, 5
ONCTL#
O
OD
14
V
SB
---
E31
GPWIO0
I/O
(PU
100
)
IN
TS
,
TS
2/14
V
SB
---
Ball
No.
Signal Name
I/O
(PU/PD)
Buffer
1
Type
Power
Rail
Configuration
Table 2-2.
432-EBGA Ball Assignment - Sorted by Ball Number (Continued)