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G
Core Logic Module
(Continued)
Table 5-20. F2: PCI Header Registers for IDE Controller Support Summary
F2 Index
Width
(Bits)
Type
Name
Reset
Value
Reference
(Table 5-35)
00h-01h
02h-03h
04h-05h
06h-07h
08h
09h-0Bh
0Ch
0Dh
0Eh
0Fh
10h-13h
16
16
16
16
8
24
8
8
8
8
32
RO
RO
R/W
RO
RO
RO
RO
RO
RO
RO
RO
Vendor Identification Register
Device Identification Register
PCI Command Register
PCI Status Register
Device Revision ID Register
PCI Class Code Register
PCI Cache Line Size Register
PCI Latency Timer Register
PCI Header Type Register
PCI BIST Register
Base Address Register 0 (F2BAR0) — Reserved for possible
future use by the Core Logic module.
Base Address Register 1 (F2BAR1) — Reserved for possible
future use by the Core Logic module.
Base Address Register 2 (F2BAR2) — Reserved for possible
future use by the Core Logic module.
Base Address Register 3 (F2BAR3) — Reserved for possible
future use by the Core Logic module.
Base Address Register 4 (F2BAR4) — Sets the base address for
the I/O mapped Bus Master IDE Registers (summarized in Table
5-21)
Reserved
Subsystem Vendor ID
Subsystem ID
Reserved
Channel 0 Drive 0 PIO Register
Channel 0 Drive 0 DMA Control Register
Channel 0 Drive 1 PIO Register
Channel 0 Drive 1 DMA Control Register
Channel 1 Drive 0 PIO Register
Channel 1 Drive 0 DMA Control Register
Channel 1 Drive 1 PIO Register
Channel 1 Drive 1 DMA Control Register
Reserved
100Bh
0502h
0000h
0280h
01h
010180h
00h
00h
00h
00h
00000000h
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14h-17h
32
RO
00000000h
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18h-1Bh
32
RO
00000000h
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1Ch-1Fh
32
RO
00000000h
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20h-23h
32
R/W
00000001h
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24h-2Bh
2Ch-2Dh
2Eh-2Fh
30h-3Fh
40h-43h
44h-47h
48h-4Bh
4Ch-4Fh
50h-53h
54h-57h
58h-5Bh
5Ch-5Fh
60h-FFh
---
16
16
---
32
32
32
32
32
32
32
32
---
---
RO
RO
---
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
---
00h
100Bh
0502h
00h
00009172h
00077771h
00009172h
00077771h
00009172h
00077771h
00009172h
00077771h
00h
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