- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98145 > ST7267C8T1/XXX (STMICROELECTRONICS) 16-BIT, MROM, 30 MHz, RISC MICROCONTROLLER, PQFP48 PDF資料下載
參數(shù)資料
| 型號： | ST7267C8T1/XXX |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 30 MHz, RISC MICROCONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, LEAD FREE, TQFP-48 |
| 文件頁數(shù)： | 23/189頁 |
| 文件大?。?/td> | 1643K |
| 代理商： | ST7267C8T1/XXX |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁當前第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁
ST7267C8 ST7267R8
119/189
MSCI ST7 INTERFACE (Cont’d)
14.2.6 ST7 Register Description
ALL THESE REGISTERS ARE IN THE ST7 ME-
MEMORY MAP AND CANNOT BE ACCESSED
BY THE MSCI CORE
MSCI CONTROL REGISTER (MCR)
Read / Write
Reset Value: 0000 0001 (01h)
Bit 7:6 = Reserved
Bit 5 = ITRIE ITR Interrupt Enable.
This bit is set and cleared by ST7 software
0: ITR interrupt disabled
1: ITR interrupt enabled
Bit 4 = STPIE Stop Interrupt Enable.
This bit is set and cleared by ST7 software
0: STOP interrupt disabled
1: STOP interrupt enabled
Bit 3 = GO Go.
This bit is set by ST7 software and cleared by
hardware. It is always read as ’0’. It generates a
pulse to launch the MSCI after it has been self-
stopped by an internal STOP instruction.
0: No effect
1: Generate a starting pulse
Bit 2 = RAMLD RAM Load.
This bit is set and cleared by ST7 software. The
MSCI must be under PC or Soft reset before start-
ing a read or write sequence. It can be written only
when PCR or SFTR is set (or when MSCI is
stopped by emulator in emulation mode)
See Section 14.2.4 and Section 14.2.4.1
0: RAM access from ST7 disabled
1: RAM access from ST7 enabled
Bit 1 = PCR Program Counter Reset.
This bit is set and cleared by ST7 software. It can
be written only when RAMLD is cleared.
0: MSCI program counter reset not forced
1: MSCI program counter forced to MPCM &
MPCL value.
Bit 0 = SFTR Soft Reset.
This bit is set and cleared by ST7 software. It can
be written only when RAMLD is cleared.
0: MSCI system reset not forced
1: MSCI system under reset.
MSCI STATUS REGISTER (MSR)
Read / Write
Reset Value: 0000 0000 (00h)
Bit 7:6 = Reserved
Bit 5 = ITR MSCI CORE ITR flag.
This bit is set by MSCI software and cleared by a
PC reset or a soft reset or by writing a ’1’ in the
CITR bit in ST7 software.
0: MSCI ITR flag not set
1: MSCI ITR flag set by an internal ITR instruction.
Bit 4 = STP MSCI CORE Stop flag.
This bit is set by MSCI software and cleared by a
PC reset or a soft reset or by writing a ’1’ in the
CSTP bit in ST7 software
0: MSCI stop flag not set
1: MSCI stop flag set by an internal STOP instruc-
tion
Bit 3:2 = Reserved
Bit 1 = CITR Clear ITR flag.
This bit is set by ST7 software to clear the MSCI
ITR flag and interrupt and reset by hardware. It is
always read as ’0’.
0: No effect
1: Clears MSCI ITR flag and interrupt if pending
Bit 0 = CSTP Clear Stop flag.
This bit is set by ST7 software to clear the MSCI
STOP flag and interrupt and reset by hardware. It
is always read as ’0’.
0: No effect
1: Clears MSCI STOP flag and interrupt if pending
Note:
To set the RAMLD bit when PCR=0 and SFTR=0,
two write accesses to MCR register are needed.
The first access must set either the SFTR bit or the
PCR bit to enable write access to RAMLD bit. The
second write access can set the RAMLD bit. Ex-
cept in emulation mode when MSCI is stopped by
emulator.
To clear the PCR bit or the SFTR bit when RAMLD
bit is set, two write accesses to MCR register are
needed. The first access to reset the RAMLD bit.
The second write access to clear PCR bit or SFTR
bit. This must be done also in emulation mode.
70
-
ITRIE
STPIE
GO
RAMLD PCR
SFTR
70
-
ITR
STP
-
CITR
CSTP
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST72774S9T1/XXX | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP44 |
| ST72E734J6D0 | 8-BIT, UVPROM, 8 MHz, MICROCONTROLLER, CDIP42 |
| ST72T774S9T1 | 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PQFP44 |
| ST7294C6B6 | 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PDIP28 |
| ST72T94C6M6 | 8-BIT, OTPROM, MICROCONTROLLER, PDSO28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST72681/R12 | 制造商:STMicroelectronics 功能描述:CONTROLLER FOR HIGH-PERFORMANCE BUS-POWERED USB 2.0 FLASH DR - Trays |
| ST72681/S13 | 制造商:STMicroelectronics 功能描述:CONTROLLER FOR HIGH-PERFORMANCE - Trays |
| ST7271 | 制造商:Panasonic Industrial Company 功能描述:IC |
| ST7271N5B1-CLF | 制造商:STMicroelectronics 功能描述: |
| ST727X4-EMU2B | 制造商:STMicroelectronics 功能描述:REALTIME EMULATOR BOARD - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。