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參數(shù)資料
| 型號： | ST7267C8T1/XXX |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 30 MHz, RISC MICROCONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, LEAD FREE, TQFP-48 |
| 文件頁數(shù)： | 7/189頁 |
| 文件大?。?/td> | 1643K |
| 代理商： | ST7267C8T1/XXX |
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ST7267C8 ST7267R8
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0: Compensation cell enabled
1: Compensation cell disabled.
Bit 0 = EOSE End Of Suspend Enabled.
This bit is set and cleared by software to enable/
disable the End Of Suspend interrupt generation.
0: EOS interrupt disabled
1: EOS interrupt enabled
Note: before enabling EOS interrupt (setting
EOSE bit), it is advised to clear the EOS bit of
EOSSR register to avoid any parasitic interrupt.
10.5.7 Programming consideration
This section describes how to control the USB de-
vice.
10.5.7.1 Soft Connect/Disconnect
The UTMI interface between the PHY and the
USB controller can be switched between normal
mode and non-driving mode by setting/clearing bit
6 of the Power register (PWRR).
When the Soft Connect/Disconnect bit is set to 1,
the PHY is placed in its normal mode and the D+/
D- lines of the USB bus are enabled. At the same
time, the USB controller is placed in ‘Powered’
state, in which it will not respond to any USB sig-
nalling except a USB reset.
10.5.8 USB reset
When a reset condition is detected on the USB,
the USB controller performs the following actions:
■ Sets FAddr to 0.
■ Sets Index to 0.
■ Flushes all endpoint FIFOs.
■ Clears all control/status registers.
■ Enables all interrupts, except Suspend.
■ Generates a Reset interrupt.
When the software receives a Reset interrupt, it
should close any open pipes and wait for bus enu-
meration to begin.
10.5.9 Suspend /Resume
When the USB device sees no activity on the USB
for 3 ms it will generate a Suspend interrupt. It is
up to the software to decide what to disable when
the USB is in Suspend mode.
Note: To decrease the consumption, refer to the
Halt mode description chapter, section 5.3 on
Software may perform “Remote Wake-up” by set-
ting the Resume bit in the Power register (bit 2).
The USB device will then send Resume signalling
on the USB to wake up the hub.
The USB may exit Suspend mode by sending
Resume signalling on the bus, this detection could
be performed differently if the clocks are active or
not in the device.
10.5.9.1 Remote wake-up
If the USB device is in Suspend mode and the soft-
ware wants to initiate a remote wake-up, it should
write to the Power register to set the Resume bit
(bit 2) to 1. Of course if the clocks are stopped, it
will need an external event (ST7 external interrupt)
to restart the clocks.
Software should leave this bit set for approximate-
ly 10 ms (minimum of 2 ms, a maximum of 15 ms)
then reset it to 0. By this time the hub should have
taken over driving Resume signalling on the USB.
Note: No Resume interrupt is generated when
software initiates a remote wake-up.
10.5.9.2 Clock active during suspend
If the Enable Suspend Mode bit in the Power reg-
ister (bit 0) is set when a Suspend interrupt is gen-
erated, the UTM will be put into Suspend mode by
the SUSPENDM line. The USB controller will,
however, remain active and therefore can detect
when Resume signalling occurs on the USB. It will
then bring the UTM out of Suspend mode and gen-
erate a Resume interrupt.
10.5.9.3 Clock inactive during suspend
When a Suspend interrupt is received, software
may put the device in Halt mode by executing the
ST7 halt instruction. In this case a specific block
"end of Suspend Block" will track any change on
UTM linestate signals. If a linestate toggles the
EOS block generates an USB End Of Suspend In-
terrupt to wake-up the ST7 from Halt.
After the clocks are restored the USB device will
detect the wake-up event (Resume or Reset).
10.5.10 Endpoint 0 handling
Endpoint 0 is the main control endpoint of the core.
As such, the routines required to service Endpoint
0 are more complicated than those required to
service other endpoints.
The software is required to handle all the Standard
Device Requests that may be received via End-
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