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參數(shù)資料
| 型號(hào)： | ST7267C8T1/XXX |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 30 MHz, RISC MICROCONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, LEAD FREE, TQFP-48 |
| 文件頁(yè)數(shù)： | 45/189頁(yè) |
| 文件大?。?/td> | 1643K |
| 代理商： | ST7267C8T1/XXX |
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ST7267C8 ST7267R8
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17 MSCI PARALLEL INTERFACE
17.1 INTRODUCTION
The MSCI Parallel Interface is a hardware block
controlled by the MSCI core. It provides fast paral-
lel communication in master mode with the follow-
ing capabilities:
■ 8 or 16-bit data width.
■ 8 control lines to output the configurable control
signal.
■ High
speed continuous data flow can be
obtained with internal double buffering.
■ 22-bit ECC Error Code correction generator for
1 bit correction in 256 byte packet.
■ Hardware Reed Solomon encoder and decoder
correcting 4 bytes in a 512-byte packet.
17.2 FUNCTIONAL DESCRIPTION
The parallel interface can be used in input or out-
put.
Three data width configurations can be used:
■ 8-bit data on first half of the 16-bit data port
■ 8-bit data on second half of the 16-bit data port
■ 16-bit data.
In output mode the parallel interface automatically
sends data on data I/O ports (8-bit or 16-bit) and
generates Write Enable or clock signals on dedi-
cated I/Os. Data is output at beginning of cycle.
In input mode the parallel interface automatically
reads data from data I/O ports (8-bit or 16-bit) and
generates Read Enable or clock signals on dedi-
cated I/Os. Data can be sampled either at the end
of each cycle or on the edge of the control signal.
The shape of the control signals, the clock fre-
quency, the control signals output ports can be
controlled with dedicated configuration registers.
note: All the control signals are generated by only
one generator and have the same shape.
Two Error Code Corrections algorithms are availa-
ble to ensure data reliability. One ECC generator
compliant with Smart Media Card specification (1-
bit correction in 256-byte packets) and one Reed
Solomon algorithm (4-byte correction in 512-byte
packets) with full hardware encoding and decod-
ing.
Figure 55. MSCI parallel Interface Block Diagram
Control signal
generator
Read/Write
Registers
Read Only
FIFO
Parallel
Interface
State
Machine
PARALLEL INTERFACE
MSCI CORE
8*16-bit
byte
swap
Communication buffers
buffer0
buffer1
FIFO
buffer
.
VCI INTERFACE
direct 128-bit
copy
8*16-bit 8*16-bit
alternate output
alternate enable
alternate output
MSCI I/O Port 1
MSCI I/O Port 2
status
ECC generator
RS encoder
RS decoder
MSCI Bus
Vectored
Bus
12
8-
bit
16
-b
it
sampling
REED SOLOMON
512 bytes
RAM
PORT1 INPUT
triggered inputs from pins
Clock
Prescaler
MSCIcoreclk
MSCIperiphclk
RSEclk
RSDclk
Flag Registers
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