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參數(shù)資料
| 型號： | ST7267C8T1/XXX |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 30 MHz, RISC MICROCONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, LEAD FREE, TQFP-48 |
| 文件頁數(shù)： | 5/189頁 |
| 文件大小： | 1643K |
| 代理商： | ST7267C8T1/XXX |
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ST7267C8 ST7267R8
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tomatically cleared when a packet of OUTMAXP
bytes has been unloaded from the OUT FIFO.
When packets of less than the maximum packet
size are unloaded, OPR will have to be cleared
manually.
Bit 6 = Reserved.
Bit 4 = DMAE DMA Enable
0: DMA request for the OUT endpoint disabled
1: DMA request for the OUT endpoint enabled.
Bit 4 = DNY Disable Nyet
Software sets this bit to disable the sending of
NYET handshakes. When set, all successfully re-
ceived OUT packets are ACK’d including at the
point at which the FIFO becomes full.
Note: This bit only has effect in High-speed mode.
In this mode it should be set for all Interrupt end-
points.
Bit 3 = DMAM DMA Mode
Two modes of operation are supported: In DMA
Mode 0 a DMA request is generated for all re-
ceived packets, together with an interrupt (if ena-
bled); In DMA Mode 1 a DMA request (but no inter-
rupt) is generated for OUT packets of size OUT-
MAXP bytes and an interrupt (but no DMA re-
quest) is generated for OUT packets of any other
size. DMAM is set by software to select the DMA
mode.
0: DMA Mode 0
1: DMA Mode 1
Bit 2:0= Reserved.
OUT
CONTROL
STATUS
REGISTER
LSB
(OUTCSRL)
OUTCSRL is the LSB of a register that provides
control and status bits for OUT transactions
through the currently-selected endpoint.
Read/Write
Reset value: 0000 0000 (00h)
Bit 7 = CDT Clear Data Toggle.
Software writes a 1 to this bit to reset the endpoint
OUT data toggle to 0.
Bit 6 = STST Sent Stall
This bit is set when a STALL handshake is trans-
mitted. Software should clear this bit.
Bit 5= SDST Send Stall
Software writes a 1 to this bit to terminate the cur-
rent transaction. The STALL handshake will be
transmitted and then this bit will be cleared auto-
matically.
Bit 4= FLFI Flush FIFO (Self clearing)
Software writes a 1 to this bit to flush the next
packet to be read from the endpoint OUT FIFO.
Note: If the FIFO contains two packets, FlushFIFO
will need to be set twice to completely clear the
FIFO.
Bit 3:2 = Reserved.
Bit 1 = FIFU FIFO full flag
This bit is set when no more packets can be load-
ed into the OUT FIFO. FIFU is cleared by hard-
ware.
Bit 0 = OPR OUT Packet Ready flag
This bit is set when a data packet has been re-
ceived. Software should clear this bit when the
packet has been unloaded from the OUT FIFO. An
interrupt is generated (if enabled) when the bit is
set.
OUT COUNT REGISTER MSB (OUTCNTRM)
Read Only
Reset value: 0000 0000 (00h)
OUTCNTRM is the MSB register that holds the
number of received data bytes in the packet in the
OUT FIFO.
Note: The value returns changes as the contents
of the FIFO change and is only valid while OPR bit
in the OUTCSRL register is set.
70
CDT
STST
SDST
FLFI
0
FIFU
OPR
70
0
OC12
OC11
OC10
OC9
OC8
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