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參數(shù)資料
| 型號(hào)： | ST7267C8T1/XXX |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 30 MHz, RISC MICROCONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, LEAD FREE, TQFP-48 |
| 文件頁(yè)數(shù)： | 69/189頁(yè) |
| 文件大?。?/td> | 1643K |
| 代理商： | ST7267C8T1/XXX |
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ST7267C8 ST7267R8
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MSCI PARALLEL INTERFACE (Cont’d)
Bit 4 = DE Decoder Enable.
This bit is set and reset by software to enable or
disable the RS decoder. If decoder is enabled,
data sent or received by parallel interface are also
sent to the decoder input. If DE is reset, data trans-
ferred with parallel interface are not taken into ac-
count by the RS decoder.
0: RS Decoder disabled
1: RS Decoder enabled
Bit 3 = EPR Encoder Parity Ready.
This bit is set by hardware when parity bits are
ready to be read from the encoder output FIFO. It
is reset by hardware when the first data of a new
data packet is received by the encoder.
0: RS Encoder parity is not ready
1: RS Encoder parity is ready
Bit 2 = FD Feed Decoder. (write only)
Write 1 in this bit to send the content of the decod-
er input FIFO to the decoder. This must be done to
provide parity symbols to the decoder in 10-bit for-
mat (eight 10-bit symbols are automatically sent
from the decoder input FIFO to the decoder cell).
The Decoder enable bit must be set before writing
1 in bit FD to have the parity symbols correctly tak-
en into account by the RS decoder.
0: No effect
1: Send parity symbols to decoder now.
Bit 1 = EE Encoder Enable.
This bit is set and reset by software to enable or
disable the RS encoder. When encoder is ena-
bled, data sent or received by the parallel interface
are also sent to the encoder input. If EE is reset,
data transferred through the parallel interface are
not taken into account by the RS encoder.
0: RS Encoder disabled.
1: RS Encoder enabled.
Bit 0 = DIFF Decoder Input FIFO Full.
This bit is set by hardware when the decoder input
FIFO is full and reset by hardware when the con-
tent of the FIFO is sent to the Decoder.
0: Decoder input FIFO not full.
1: Decoder input FIFO full.
REED SOLOMON DECODER FIFO REGISTER (RDFR)
Read / Write
Reset Value: 0000 0000 0000 0000 (0000h).
Bit [15:0] = DFD Decoder FIFO Data.
Writing into this register adds a word into the RS
decoder input FIFO (used to send parity symbols
in 10-bit format to the decoder)
Reading this register returns a 16-bit word from
the RS decoder Output FIFO. If RS decoder Out-
put FIFO is empty when read, the MSCI core is fro-
zen until the FIFO is ready to be read.
REED SOLOMON ENCODER FIFO REGISTER (REFR)
Read
Reset Value: 0000 0000 0000 0000 (0000h).
Bit [15:0] = EFD Encoder FIFO Data.
Reading this register returns a 16-bit word from
the RS encoder Output FIFO. This FIFO contains
5 16-bit words that must all be read in order to let
the FIFO pointer pointing on the first word for next
data packet. Reading this register when FIFO is
not ready does NOT freeze the MSCI CPU.
15
8
7
0
DFD15 DFD14 DFD13 DFD12 DFD11 DFD10 DFD9
DFD8
DFD7
DFD6
DFD5
DFD4
DFD3
DFD2
DFD1
DFD0
15
8
7
0
EFD15 EFD14 EFD13 EFD12 EFD11 EFD10 EFD9
EFD8
EFD7
EFD6
EFD5
EFD4
EFD3
EFD2
EFD1
EFD0
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