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參數(shù)資料
| 型號(hào)： | ST7267C8T1/XXX |
| 廠(chǎng)商： | STMICROELECTRONICS |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 30 MHz, RISC MICROCONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, LEAD FREE, TQFP-48 |
| 文件頁(yè)數(shù)： | 58/189頁(yè) |
| 文件大?。?/td> | 1643K |
| 代理商： | ST7267C8T1/XXX |
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ST7267C8 ST7267R8
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MSCI PARALLEL INTERFACE (Cont’d)
17.8 REED SOLOMON DECODER
The Reed Solomon decoder is a hardware system
that can detect and correct 4 erroneous bytes in a
512-byte data packet received (or sent) by the par-
allel interface. It must receive packets made of 520
10-bit symbols (512 data symbols followed by 8
parity symbols). See Figure 67
The data symbols are provided to the decoder by
the parallel interface when the decoder is enabled.
They are converted to 10 bit by adding 2 most sig-
nificant bits and forcing them to 0. The parity sym-
bols must be sent to the decoder through a dedi-
cated input FIFO. This FIFO makes the conversion
from 16-bit words to 10-bit words for the parity
symbols.
After receiving a complete packet of 520 symbols,
the Reed Solomon decoder automatically starts its
algorithm. After a few cycles it is able to indicate
whether the packet is corrupted with the "errors"
and "errors_valid" flags. If the packet contains er-
rors, the correction algorithm is automatically start-
ed. After approximately 20 MSCI cycles (depends
on the error) the Reed Solomon is ready to output
512-byte corrected data packed. Data output of
the decoder can be read through a dedicated out-
put FIFO. See Figure 68
The Input FIFO can be filled at any time by the
MSCI core. When the RS decoder has received all
the data bytes, the MSCI program must send the
redundant symbols to the decoder. To do this the
MSCI software must write 1 in the "Feed Decoder"
bit of the RSCSR register. This sends the content
of the input FIFO in 10-bit format to the decoder.
The redundancy words must be sent in the
same order and with the same byte ordering as
they were read from the encoder output!
The output FIFO is automatically filled by the de-
coder when the errors are corrected (this only hap-
pens if an error was detected). The MSCI software
can recover the 512-byte data packet from this
output FIFO by series of eight 16-bit words.
Note: the same register is used to access input
FIFO and output FIFO of the RS decoder. Writing
into this register store data in the input FIFO, read-
ing this register returns data from the output FIFO.
Figure 67. Reed Solomon 520-symbol frame.
Figure 68. Reed Solomon decoder implementation (When RS decoder enable = 1)
symbols
8 parity
520 symbols
2 MSB of
data symbols
forced to 0
10 bits
512 data bytes
Word 7
Word 6
Word 5
Word 4
Word 3
Word 2
Word 1
Word 0
COM. BUFFER (0 or 1)
word/byte
conversion
ECC swap bytes
RS decoder
Input or Output
mode
previous data word
Status flags
received from I/Os
Decoder output FIFO
(8*16-bit)
Decoder input FIFO
(5*16-bit)
MSCI
16-b
it
B
U
S
512byte
RS decoder
RAM
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