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參數(shù)資料
| 型號(hào)： | ST7267C8T1/XXX |
| 廠商： | STMICROELECTRONICS |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 30 MHz, RISC MICROCONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, LEAD FREE, TQFP-48 |
| 文件頁(yè)數(shù)： | 4/189頁(yè) |
| 文件大小： | 1643K |
| 代理商： | ST7267C8T1/XXX |
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ST7267C8 ST7267R8
101/189
Bit 4 = SDST Send Stall
The CPU writes a 1 to this bit to issue a a STALL
handshake to an IN token. The CPU clears this bit
to terminate the stall condition.
Bit 3 = FLFI Flush FIFO (Self clearing)
Software writes a 1 to this bit to flush the next
packet to be transmitted from the endpoint IN
FIFO. The FIFO pointer is reset and the IPR bit is
cleared.
Note: If the FIFO contains two packets, FlushFIFO
will need to be set twice to completely clear the
FIFO
Bit 2 = UNDR Under Run
This bit is set when a NAK is returned in response
to an IN token. Software should clear this bit.
Bit 1 = FINE FIFO not empty
This bit is set when there is at least 1 packet in the
IN FIFO.
Bit 0 = IPR In Packet Ready
Software sets this bit after loading a data packet
into the FIFO. It is cleared automatically when the
data packet has been transmitted. If the FIFO is
double-buffered, it is also automatically cleared
when there is space for a second packet in the
FIFO. An interrupt is generated (if enabled) when
this bit is cleared.
OUT MAX PACKET REGISTER MSB (OUTMAX-
PRM)
Read/Write
Reset value: 0000 0000 (00h)
This register defines the most significant byte of
the maximum payload transmitted in a single
transaction.
Bits 7:3 = Reserved.
Bit 2:0= OMP[10:8] OUT Max Packet.
OUT MAX PACKET REGISTER LSB (OUTMAX-
PRL)
Read/Write
Reset value: 0000 0000 (00h)
This register defines the least significant byte of
the maximum payload transmitted in a single
transaction.
Bits 7:0 = OMP[7:0] OUT Max Packet.
OUTMAXPR are registers that define the maxi-
mum amount of data that can be transferred
through the selected OUT endpoint in a single
frame / microframe (High-speed transfers). There
is an OUTMAXP register for each OUT endpoint
(except Endpoint 0).
The value written to the OUTMAXPRx registers
should match the wMaxPacketSize field of the
Standard Endpoint Descriptor for the associated
endpoint (see Universal Serial Bus Specification
Revision 2.0, Chapter 9). A mismatch could cause
unexpected results.
The total amount of data represented by the value
written to these registers (maximum payload
×
maximum number of transactions) must not ex-
ceed the FIFO size for the OUT endpoint, and
should not exceed half the FIFO size if double-
buffering is required.
OUT
CONTROL
STATUS REGISTER MSB
(OUTCSRM)
OUTCSRM is the MSB of a register that provides
control and status bits for OUT transactions
through the currently-selected endpoint.
Read/Write
Reset value: 0000 0000 (00h)
Bit 7 = ACLR Auto Clear.
If software sets this bit then the OPR bit will be au-
70
00
0
OMP1
0
OMP9 OMP8
70
OMP7 OMP6 OMP5 OMP4 OMP3 OMP2 OMP1 OMP0
70
ACLR
o
DMAE
DNY
DMAM
0
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