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8.7.4
PLL1 Controller Input and Output Clock Electrical Data/Timing
CLKIN1
2
3
4
4
5
1
SYSCLK4
3
4
4
2
TMS320TCI6482
Communications Infrastructure Digital Signal Processor
SPRS246F–APRIL 2005–REVISED MAY 2007
Table 8-29. Timing Requirements for CLKIN1 Devices
(1)(2)(3)
(see
Figure 8-21
)
-850
A-1000
-1000
PLL MODES
x1 (Bypass), x15,
x20, x25, x30, x32
MIN
15
0.4C
0.4C
NO.
UNIT
MAX
30.3
1
2
3
4
5
t
c(CLKIN1)
t
w(CLKIN1H)
t
w(CLKIN1L)
t
t(CLKIN1)
t
J(CLKIN1)
The reference points for the rise and fall transitions are measured at 3.3 V V
MAX and V
IH
MIN.
For more details on the PLL multiplier factors (x1 [BYPASS], x 15, x20, x25, x30, x32), see
Section 8.7.1.2
,
PLL1 Controller Operating
Modes
.
C =
CLKIN1
cycle time in ns. For example, when CLKIN1 frequency is 50 MHz, use C = 20 ns.
The PLL1 multiplier factors (x1 [BYPASS], x 15, x20, x25, x30, x32) further limit the MIN and MAX values for t
. For more
detailed information on these limitations, see
Section 8.7.1.1
,
Internal Clocks and Maximum Operating Frequencies
.
Cycle time, CLKIN1
(4)
Pulse duration, CLKIN1 high
Pulse duration, CLKIN1 low
Transition time, CLKIN1
Period jitter (peak-to-peak), CLKIN1
ns
ns
ns
ns
ps
1.2
100
(1)
(2)
(3)
(4)
Figure 8-21. CLKIN1 Timing
Table 8-30. Switching Characteristics Over Recommended Operating Conditions for SYSCLK4
[CPU/8 - CPU/12]
(1)(2)
(see
Figure 8-22
)
-850
A-1000
-1000
NO.
PARAMETER
UNIT
MIN
4P – 0.7
4P – 0.7
MAX
6P + 0.7
6P + 0.7
2
3
4
t
w(CKO3H)
t
w(CKO3L)
t
t(CKO3)
Pulse duration, SYSCLK4 high
Pulse duration, SYSCLK4 low
Transition time, SYSCLK4
ns
ns
ns
1
(1)
(2)
The reference points for the rise and fall transitions are measured at 3.3 V V
OL
MAX and V
OH
MIN.
P = 1/CPU clock frequency in nanoseconds (ns)
Figure 8-22. SYSCLK4 Timing
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