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AECLKOUT
ACEx
ABE[7:0]
AEA[19:0]/
ABA[1:0]
AED[63:0]
AAOE/ASOE
(A)
AR/W
AAWE/ASWE
(A)
AARDY
(B)
Byte Enables
Address
Read Data
Hold = 1
2
Strobe = 4
Setup = 1
2
2
4
10
10
1
1
1
3
A AAOE/ASOE and AAWE/ASWE operate as AAOE (identified under select signals) and AAWE, respectively, during asynchronous
memory accesses.
B Polarity of the AARDY signal is programmable through the AP field of the EMIFA Async Wait Cycle Configuration register (AWCC).
DEASSERTED
TMS320TCI6482
Communications Infrastructure Digital Signal Processor
SPRS246F–APRIL 2005–REVISED MAY 2007
Table 8-45. Switching Characteristics Over Recommended Operating Conditions for Asynchronous
Memory Cycles for EMIFA Module
(1)(2)(3)
(see
Figure 8-33
and
Figure 8-34
)
-850
A-1000
-1000
MIN
NO.
PARAMETER
UNIT
MAX
1
2
10
11
12
13
t
osu(SELV-AOEL)
t
oh(AOEH-SELIV)
t
d(EKOH-AOEV)
t
osu(SELV-AWEL)
t
oh(AWEH-SELIV)
t
d(EKOH-AWEV)
E = AECLKOUT period in ns for EMIFA
RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters
are programmed via the EMIFA CE Configuration registers (CEnCFG).
Select signals for EMIFA include: ACEx, ABE[7:0], AEA[19:0], ABA[1:0]; and for EMIFA writes, also include AR/W, AED[63:0].
Output setup time, select signals valid to AAOE low
Output hold time, AAOE high to select signals invalid
Delay time, AECLKOUT high to AAOE valid
Output setup time, select signals valid to AAWE low
Output hold time, AAWE high to select signals invalid
Delay time, AECLKOUT high to AAWE valid
RS * E – 1.5
RS * E – 1.9
ns
ns
ns
ns
ns
ns
1
7
WS * E – 1.7
WH * E – 1.8
1.3
7.1
(1)
(2)
(3)
Figure 8-33. Asynchronous Memory Read Timing for EMIFA
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