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8.8.2
PLL2 Controller Memory Map
8.8.3
PLL2 Controller Register Descriptions
TMS320TCI6482
Communications Infrastructure Digital Signal Processor
SPRS246F–APRIL 2005–REVISED MAY 2007
The memory map of the PLL2 controller is shown in
Table 8-32
. Note that only registers documented here
are accessible on the TMS320TCI6482. Other addresses in the PLL2 controller memory map should not
be modified.
Table 8-32. PLL2 Controller Registers
HEX ADDRESS RANGE
029C 0000 - 029C 0114
029C 0118
029C 011C - 029C 0134
029C 0138
029C 013C
029C 0140
029C 0144
029C 0148
029C 014C
029C 0150
029C 0154 - 029C 0190
029C 0194 - 029C 01FF
029C 0200 - 029C FFFF
ACRONYM
-
PLLDIV1
-
PLLCMD
PLLSTAT
ALNCTL
DCHANGE
-
-
SYSTAT
-
-
-
DESCRIPTION
Reserved
PLL Controller Divider 1 Register
Reserved
PLL Controller Command Register
PLL Controller Status Register
PLL Controller Clock Align Control Register
PLLDIV Ratio Change Status Register
Reserved
Reserved
SYSCLK Status Register
Reserved
Reserved
Reserved
This section provides a description of the PLL2 controller registers. For details on the operation of the PLL
controller module, see the
TMS320TCI648x DSP Software-Programmable Phase-Locked Loop (PLL)
Controller User's Guide
(literature number
SPRU806
).
NOTE:
The PLL2 controller registers can only be accessed using the CPU or the emulator.
Not all of the registers documented in the
TMS320TCI648x DSP Software-Programmable Phase-Locked
Loop (PLL) Controller User's Guide
(literature number
SPRU806
) are supported on the TMS320TCI6482.
Only those registers documented in this section are supported. Furthermore, only the bits within the
registers described here are supported. You should not write to any reserved memory location or change
the value of reserved bits.
C64x+ Peripheral Information and Electrical Specifications
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