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8.11.3 I2C Electrical Data/Timing
TMS320TCI6482
Communications Infrastructure Digital Signal Processor
SPRS246F–APRIL 2005–REVISED MAY 2007
8.11.3.1
Inter-Integrated Circuits (I2C) Timing
Table 8-52. Timing Requirements for I2C Timings
(1)
(see
Figure 8-42
)
-850
A-1000
-1000
NO.
UNIT
STANDARD MODE
MIN
10
FAST MODE
MIN
2.5
MAX
MAX
1
t
c(SCL)
Cycle time, SCL
Setup time, SCL high before SDA low (for a
repeated START condition)
Hold time, SCL low after SDA low (for a
START and a repeated START condition)
Pulse duration, SCL low
Pulse duration, SCL high
Setup time, SDA valid before SCL high
Hold time, SDA valid after SCL low (For I
2
C
bus devices)
Pulse duration, SDA high between STOP and
START
conditions
Rise time, SDA
Rise time, SCL
Fall time, SDA
Fall time, SCL
Setup time, SCL high before SDA high (for
STOP condition)
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
μ
s
2
t
su(SCLH-SDAL)
4.7
0.6
μ
s
3
t
h(SCLL-SDAL)
4
0.6
μ
s
4
5
6
t
w(SCLL)
t
w(SCLH)
t
su(SDAV-SDLH)
4.7
1.3
0.6
μ
s
μ
s
ns
4
250
100
(2)
7
t
h(SDA-SDLL)
0
(3)
0
(3)
0.9
(4)
μ
s
8
t
w(SDAH)
4.7
1.3
μ
s
9
t
r(SDA)
t
r(SCL)
t
f(SDA)
t
f(SCL)
1000
1000
300
300
20 + 0.1C
b(5)
20 + 0.1C
b(5)
20 + 0.1C
b(5)
20 + 0.1C
b(5)
300
300
300
300
ns
ns
ns
ns
10
11
12
13
t
su(SCLH-SDAH)
4
0.6
μ
s
14
15
t
w(SP)
C
b(5)
0
50
400
ns
pF
400
(1)
The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
A Fast-mode I
2
C-bus device can be used in a Standard-mode I
2
C-bus system, but the requirement t
≥
250 ns must then
be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line t
max + t
su(SDA-SCLH)
= 1000 + 250 = 1250 ns
(according to the Standard-mode I
2
C-Bus Specification) before the SCL line is released.
A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
IHmin
of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
The maximum t
has only to be met if the device does not stretch the low period [t
] of the SCL signal.
C
b
= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
(2)
(3)
(4)
(5)
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