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TMS320TCI6482
Communications Infrastructure Digital Signal Processor
SPRS246F–APRIL 2005–REVISED MAY 2007
Table 8-112. RapidIO Control Registers (continued)
HEX ADDRESS RANGE
02D0 045C
02D0 0460
02D0 0464
02D0 0468
02D0 046C
02D0 0470
02D0 0474
02D0 0478
02D0 047C
02D0 0480 - 02D0 04FC
02D0 0500
02D0 0504
02D0 0508
02D0 050C
02D0 0510
02D0 0514
02D0 0518
02D0 051C
02D0 0520
02D0 0524
02D0 0528
02D0 052C
02D0 0530
02D0 0534
02D0 0538
02D0 053C
02D0 0540 - 02D0 057C
02D0 0580
02D0 0584
02D0 0588
02D0 058C
02D0 0590
02D0 0594
02D0 0598
02D0 059C
02D0 05A0
02D0 05A4
02D0 05A8
02D0 05AC
02D0 05B0
02D0 05B4
02D0 05B8
02D0 05BC
02D0 05D0 - 02D0 05FC
02D0 0600
02D0 0604
02D0 0608
ACRONYM
REGISTER NAME
RIO_LSU3_FLOW_MASKS2
RIO_LSU4_REG0
RIO_LSU4_REG1
RIO_LSU4_REG2
RIO_LSU4_REG3
RIO_LSU4_REG4
RIO_LSU4_REG5
RIO_LSU4_REG6
RIO_LSU4_FLOW_MASKS3
-
RIO_QUEUE0_TXDMA_HDP
RIO_QUEUE1_TXDMA_HDP
RIO_QUEUE2_TXDMA_HDP
RIO_QUEUE3_TXDMA_HDP
RIO_QUEUE4_TXDMA_HDP
RIO_QUEUE5_TXDMA_HDP
RIO_QUEUE6_TXDMA_HDP
RIO_QUEUE7_TXDMA_HDP
RIO_QUEUE8_TXDMA_HDP
RIO_QUEUE9_TXDMA_HDP
RIO_QUEUE10_TXDMA_HDP
RIO_QUEUE11_TXDMA_HDP
RIO_QUEUE12_TXDMA_HDP
RIO_QUEUE13_TXDMA_HDP
RIO_QUEUE14_TXDMA_HDP
RIO_QUEUE15_TXDMA_HDP
-
RIO_QUEUE0_TXDMA_CP
RIO_QUEUE1_TXDMA_CP
RIO_QUEUE2_TXDMA_CP
RIO_QUEUE3_TXDMA_CP
RIO_QUEUE4_TXDMA_CP
RIO_QUEUE5_TXDMA_CP
RIO_QUEUE6_TXDMA_CP
RIO_QUEUE7_TXDMA_CP
RIO_QUEUE8_TXDMA_CP
RIO_QUEUE9_TXDMA_CP
RIO_QUEUE10_TXDMA_CP
RIO_QUEUE11_TXDMA_CP
RIO_QUEUE12_TXDMA_CP
RIO_QUEUE13_TXDMA_CP
RIO_QUEUE14_TXDMA_CP
RIO_QUEUE15_TXDMA_CP
-
RIO_QUEUE0_RXDMA_HDP
RIO_QUEUE1_RXDMA_HDP
RIO_QUEUE2_RXDMA_HDP
LSU3 Congestion Control Flow Mask Register
LSU4 Control Register 0
LSU4 Control Register 1
LSU4 Control Register 2
LSU4 Control Register 3
LSU4 Control Register 4
LSU4 Control Register 5
LSU4 Control Register 6
LSU4 Congestion Control Flow Mask Register
Reserved
Queue Transmit DMA Head Descriptor Pointer Register 0
Queue Transmit DMA Head Descriptor Pointer Register 1
Queue Transmit DMA Head Descriptor Pointer Register 2
Queue Transmit DMA Head Descriptor Pointer Register 3
Queue Transmit DMA Head Descriptor Pointer Register 4
Queue Transmit DMA Head Descriptor Pointer Register 5
Queue Transmit DMA Head Descriptor Pointer Register 6
Queue Transmit DMA Head Descriptor Pointer Register 7
Queue Transmit DMA Head Descriptor Pointer Register 8
Queue Transmit DMA Head Descriptor Pointer Register 9
Queue Transmit DMA Head Descriptor Pointer Register 10
Queue Transmit DMA Head Descriptor Pointer Register 11
Queue Transmit DMA Head Descriptor Pointer Register 12
Queue Transmit DMA Head Descriptor Pointer Register 13
Queue Transmit DMA Head Descriptor Pointer Register 14
Queue Transmit DMA Head Descriptor Pointer Register 15
Reserved
Queue Transmit DMA Completion Pointer Register 0
Queue Transmit DMA Completion Pointer Register 1
Queue Transmit DMA Completion Pointer Register 2
Queue Transmit DMA Completion Pointer Register 3
Queue Transmit DMA Completion Pointer Register 4
Queue Transmit DMA Completion Pointer Register 5
Queue Transmit DMA Completion Pointer Register 6
Queue Transmit DMA Completion Pointer Register 7
Queue Transmit DMA Completion Pointer Register 8
Queue Transmit DMA Completion Pointer Register 9
Queue Transmit DMA Completion Pointer Register 10
Queue Transmit DMA Completion Pointer Register 11
Queue Transmit DMA Completion Pointer Register 12
Queue Transmit DMA Completion Pointer Register 13
Queue Transmit DMA Completion Pointer Register 14
Queue Transmit DMA Completion Pointer Register 15
Reserved
Queue Receive DMA Head Descriptor Pointer Register 0
Queue Receive DMA Head Descriptor Pointer Register 1
Queue Receive DMA Head Descriptor Pointer Register 2
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C64x+ Peripheral Information and Electrical Specifications
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