參數(shù)資料
型號： TVP3025-175
廠商： Texas Instruments, Inc.
英文描述： Video Interface PALETTE(三PLL，視頻接口調(diào)色器)
中文描述： 視頻接口盒（三鎖相環(huán)，視頻接口調(diào)色器）
文件頁數(shù)： 12/99頁
文件大?。?/td> 663K
代理商： TVP3025-175
1–6
1.5
Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME
HSYNCOUT
NO.
67
O
(TTL
compatible)
Horizontal sync output after pipeline delay. For system mode the output
polarity can be programmed using the general-control register, but for
the VGA mode the output carries the same polarity as the input.
Analog current outputs. These outputs can drive a 37.5-
load directly
(doubly terminated 75-
line), thus eliminating the requirement for any
external buffering.
IOR, IOG,
IOB
70, 72, 74
O
I/O0–I/O4
58–62
I/O
(TTL
compatible)
Software programmable I/O terminals that can be used to control
external devices.
LCLK
123
I
(TTL
compatible)
Pixel-port-latch clock input. LCLK is used to latch pixel-bus-input data.
It can also be used to latch the blank and sync inputs if selected by the
miscellaneous-control register bit 6.
MCLK
121
O
(TTL
compatible)
Memory clock output. User programmable frequency synthesis PLL
output.
MODE1
39
I
(TTL
compatible)
Register map select at reset. If this terminal is a logic high around the
positive edge of RESET, the device assumes the BT485 register
emulation map reset default states. It also initiates decoding into the
TVP3025 control registers and the BT485 register access monitoring.
If the terminal is a logic low at reset, TVP3025 register map reset
defaults are assumed. This mode reset function also works with the built
in software reset function. This terminal is internally pulled down so that
TVP3025 register default settings result if the terminal is not connected.
MODE2
40
I
(TTL
compatible)
Register select 4 inversion control. If this terminal is held low, the RS4
input is inverted. This causes the BT485 register map to use addresses
0–F instead of 10–1F and the TVP3025 register map to use addresses
10–17 instead of 0–7. This terminal is internally pulled up so no
inversion results if the terminal is not connected.
PCLKOUT
144
O
(TTL
compatible)
Pixel clock PLL output. To enable pixel clock PLL output on the
PCLKOUT terminal, the pixel clock P value register bit 3 must be set to
logic 1. This output is independent of the dot clock selected in the input-
clock-selection register.
PLLGND
145
I
(TTL
compatible)
PLL ground. PLLGND should be provided from the GND plane through
a ferrite bead and decoupled to the PLLVDD supply.
PLLVDD
1, 2, 146
I
(TTL
compatible)
PLL supply. One external voltage regulator is recommended to supply
power to the three integrated PLLs. The PLLVDD supply should be
decoupled to PLLGND.
OVS
96
I
(TTL
compatible)
Overscan input. OVS is used to create custom screen borders.
PSEL
97
I
(TTL
compatible)
Port select. PSEL provides the capability of VGA or overlay windows in
a direct color background on a pixel-by-pixel basis. This function is not
supported for BT485 mode operation.
NOTE: All unused inputs should be tied to a logic level and not be allowed to float.
相關(guān)PDF資料
PDF描述
TVP3030-175 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
TVP3030-220 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
TVP3030-250 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
TVP3409-170 Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS)
TVP3409-135 Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TVP3025-175PCE 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3025-220MDN 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3025-220PCE 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC)
TVP3026 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3026-135AMDN 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
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