參數(shù)資料
型號(hào): TVP3025-175
廠商: Texas Instruments, Inc.
英文描述: Video Interface PALETTE(三PLL,視頻接口調(diào)色器)
中文描述: 視頻接口盒(三鎖相環(huán),視頻接口調(diào)色器)
文件頁(yè)數(shù): 51/99頁(yè)
文件大?。?/td> 663K
代理商: TVP3025-175
2–37
2.3.13.3 Identification Code
An ID register with a hardwired code is provided that can be used as a software verification for different
versions of the system design. The ID code in the TVP3025 is static and may be read without consideration
to the dot clock or video signals. The ID register is read through the indirect register map [see Table 2–3,
index (3F hex)].
The value defined for the TVP3025 is 25 (hex).
2.3.14
The general-purpose (GP) I/O registers and output terminals provide a means of controlling external
functions such as external phase-locked loops (PLLs) through the TVP3025 microinterface. The 8-bit
general-purpose I/O data register [index 2B (hex)] has five of its bit locations (D0–D4) tied to external I/O
terminals (I/O0–I/O4). The other three bits (D5–D7) can be used for general data storage and do not affect
any other circuitry. The general-purpose I/O data register is controlled by the general-purpose I/O control
register [index 2A (hex)]. GP I/O control register bits IOC0–IOC4 control whether the corresponding
general-purpose I/O terminals are configured as inputs or outputs. The reset default condition is for GP I/O
control register bits IOC0–IOC4 = logic 0, which configures terminals I/O0–I/O4 as inputs. If any of the
GP I/O control register bits are set to a logic 1, the corresponding I/O terminals are configured as outputs.
General-Purpose I/O Registers and Terminals
The general-purpose I/O control register, data register, and terminal relationships are shown in the following
table.
DATA BIT
D3
IOC3
D7
X
D6
X
D5
X
D4
IOC4
D2
IOC2
D1
IOC1
D0
IOC0
General-Purpose I/O Control Register
General-Purpose I/O Data Register
X
X
X
D4
D3
D2
D1
D0
General-Purpose I/O Terminal
I/O4
I/O3
I/O2
I/O1
I/O0
NOTE: In BT485 mode, GP I/O4 and IOC4 are controlled through command register 4. See Section 2.4.15.5.
2.3.15
There are two ways to reset the TVP3025. The RESET input terminal can be used to perform a hardware
reset. Alternatively, the device has an integrated software reset function. The hardware and software reset
functions work with the MODE1 input terminal to reset the device to either the BT485 or TVP3025 default
modes of operation. For TVP3025 operation, the MODE1 input terminal should be low when the reset
occurs. For proper BT485 mode register translation after a reset, the microinterface should not be accessed
for 30
μ
s.
Reset
A hardware reset is initiated by pulling the RESET input terminal low. When RESET is pulled low all
TVP3025 registers go to default states. This reset is asynchronous, and any glitch on this terminal could
change the intended register setup. The default state at reset is VGA mode, and all default register settings
are given in Table 2–3. If a reset is desired at power up, an external resistor, capacitor, and diode network
can be connected to the RESET terminal (see Figure A–1 for a typical circuit). If TTL logic is employed to
provide the signal to the RESET terminal, a pull up resistor should be used to make sure that CMOS levels
are achieved.
For a software reset, anytime the reset register (FF (hex) on the indirect register map) is written to, all
registers are initialized to TVP3025 default settings. Any data can be written into the reset register to cause
this reset to occur.
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PDF描述
TVP3030-175 Video Interface PALETTE Exract(1600×1200,24位真彩色視頻接口調(diào)色器)
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