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參數(shù)資料
| 型號： | TVP3025-175 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface PALETTE(三PLL，視頻接口調(diào)色器) |
| 中文描述： | 視頻接口盒（三鎖相環(huán)，視頻接口調(diào)色器） |
| 文件頁數(shù)： | 27/99頁 |
| 文件大?。?/td> | 663K |
| 代理商： | TVP3025-175 |
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2–13
set to logic 1 (default), use of SCLK is assumed and internal pipeline delay is added to sync and blank to
account for the delay in the generation of SCLK. If auxiliary control register 3 is set to logic 0, then this
pipeline delay is not added, and SCLK should not be used.
2.3.7.1
The SCLK signal which is generated in the TVP3025 is intended to be directly connected to VRAM, providing
the shift clock to clock data from VRAM onto the TVP3025 pixel input port. The RCLK signal must be used
as the timing reference to clock pixel data into this port. Therefore, RCLK is typically directly tied back to
LCLK, or LCLK can be a delayed version of RCLK within the timing requirements of the TVP3025. The SCLK
timing mode of frame buffer latching is similar to the operation of the TLC3407x VIPs and the same as the
TVP3020 VIP device.
Frame Buffer Timing Using SCLK
The internal TVP3025 blank signal is generated from either VGABL or SYSBL, depending on whether the
VGA port is enabled (multiplex-control register 2 (MCR2) bit 7 = logic 1) or disabled (MCR2 bit 7 = logic 0).
The rising edge of CLK0 is used to latch VGABL when the VGA port is enabled. Unlike the TVP3020, SYSBL
can be sampled by either LCLK or VCLK when the VGA port is disabled. The reset default in the TVP3020
mode is for SYSBL to be sampled on the falling edge of VCLK (miscellaneous-control register
bit 6 = logic 0). If miscellaneous-control register (index 001E) bit 5 is set to logic 1, then the VCLK polarity
is inverted, and SYSBL is sampled on the rising edge of VCLK. To latch SYSBL on the rising edge of LCLK
(same timing as the pixel port data on P0–P63), miscellaneous-control register bit 6 should be set to a
logic 1.
When the internal blank signal becomes active, SCLK is disabled as soon as possible. For example, if SCLK
is high when the sampled SYSBL goes low, SCLK is allowed to complete the clock cycle and return to the
low state. SCLK is then held low until the sampled SYSBL signal goes back high. At this time, SCLK is
enabled to clock the first pixel data valid from VRAM. The TVP3025 video blanking circuitry is designed with
sufficient pipeline delay to allow the internal sampled SYSBL and VGABL signals to align with the pipelined
RGB data to the video DACs.
The SCLK control timing is designed to interface directly with the external VRAM. The shift register in the
system VRAM is supposed to be updated during the blank active period. When the SYSBL input is sampled
system, the VRAM shift clock (SCLK) is restarted to clock the VRAM and enable the first group of pixel data
to appear on the pixel bus, as well as at the TVP3025 pixel input port. The second SCLK causes the VRAM
shift register to shift out the second group of data. At the same time, LCLK latches the first group of pixel
data into the TVP3025 (refer to Figures 2–3 and 2–4 for detailed timing diagrams).
The RCLK/SCLK phase relationship is designed such that timing specifications are satisfied for the case
where SCLK is driving a typical 2-MB VRAM load and RCLK is connected to LCLK. If an external buffer is
required on SCLK so that it can drive a larger load, a similar buffer can be placed on RCLK to match the
signal delay before connecting to LCLK. However, the delay from LCLK to RCLK cannot exceed one RCLK
period (7 ns). Refer to the timing parameter specifications for more details.
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PDF描述 |
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| TVP3030-175 | Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器) |
| TVP3030-220 | Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器) |
| TVP3030-250 | Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP3025-175PCE | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3025-220MDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3025-220PCE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| TVP3026 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3026-135AMDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
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